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參數(shù)資料
| 型號(hào)： | LT1767EMS8#TR-3.3 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 3 A SWITCHING REGULATOR, 1500 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | PLASTIC, MSOP-8 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 232K |
| 代理商： | LT1767EMS8#TR-3.3 |
11
LT1767/LT1767-1.8/
LT1767-2.5/LT1767-3.3/LT1767-5
APPLICATIONS INFORMATION
WU
U
SYNCHRONIZATION
The SYNC pin, is used to synchronize the internal oscilla-
tor to an external signal. The SYNC input must pass from
a logic level low, through the maximum synchronization
threshold with a duty cycle between 20% and 80%. The
input can be driven directly from a logic level output. The
synchronizing range is equal to
initial operating frequency
up to 2MHz. This means that
minimum practical sync
frequency is equal to the worst-case
high self-oscillating
frequency (1.4MHz), not the typical operating frequency
of 1.25MHz. Caution should be used when synchronizing
above 1.6MHz because at higher sync frequencies the
amplitude of the internal slope compensation used to
prevent subharmonic switching is reduced. This type of
subharmonic switching only occurs at input voltages less
than twice output voltage. Higher inductor values will tend
to eliminate this problem. See Frequency Compensation
section for a discussion of an entirely different cause of
subharmonic switching before assuming that the cause is
insufficient slope compensation. Application Note 19 has
more details on the theory of slope compensation.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency, switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
in Figure 5, must be kept as short as possible. This is
implemented in the suggested layout of Figure 6. Shorten-
ing this path will also reduce the parasitic trace inductance
of approximately 25nH/inch. At switch off, this parasitic
inductance produces a flyback spike across the LT1767
switch. When operating at higher currents and input
voltages, with poor layout, this spike can generate volt-
ages across the LT1767 that may exceed its absolute
maximum rating. A ground plane should always be used
under the switcher circuitry to prevent interplane coupling
and overall noise.
The VC and FB components should be kept as far away as
possible from the switch and boost nodes. The LT1767
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic like oscillation.
Board layout also has a significant effect on thermal
resistance. Pin 4, GND, is a continuous copper plate that
runs under the LT1767 die. This is the best thermal path
for heat out of the package. Reducing the thermal resis-
tance from Pin 4 onto the board will reduce die tempera-
ture and increase the power capability of the LT1767. This
is achieved by providing as much copper area as possible
around this pin. Adding multiple solder filled feedthroughs
under and around Pin 4 to the ground plane will also help.
Similar treatment to the catch diode and coil terminations
will prevent any additional heating effects.
Figure 5. High Speed Switching Path
1767 F05
5V
L1
SW
VIN
LT1767
D1
C1
C3
VIN
HIGH
FREQUENCY
CIRCULATING
PATH
LOAD
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