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參數(shù)資料
| 型號(hào)： | LT1782HS5#TRM |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP R-R IN/OUT TSOT-23-5 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Over-The-Top® |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 0.075 V/µs |
| 增益帶寬積： | 225kHz |
| 電流 - 輸入偏壓： | 8nA |
| 電壓 - 輸入偏移： | 500µV |
| 電流 - 電源： | 45µA |
| 電流 - 輸出 / 通道： | 30mA |
| 電壓 - 電源，單路/雙路(±)： | 2.5 V ~ 18 V，±1.25 V ~ 9 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-5 細(xì)型，TSOT-23-5 |
| 供應(yīng)商設(shè)備封裝： | TSOT-23-5 |
| 包裝： | 剪切帶 (CT) |
| 產(chǎn)品目錄頁(yè)面： | 1319 (CN2011-ZH PDF) |
| 其它名稱： | LT1782HS5 LT1782HS5#TRMCT LT1782HS5-ND |
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LT1782
11
1782fc
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current
vs Shutdown Voltage
Large-Signal Response
Small-Signal Response
APPLICATIONS INFORMATION
Supply Voltage
The positive supply pin of the LT1782 should be bypassed
with a small capacitor (typically 0.1F) within an inch of
the pin. When driving heavy loads, an additional 4.7F
electrolytic capacitor should be used. When using split
supplies, the same is true for the negative supply pin.
The LT1782 is protected against reverse battery voltages
up to 18V. In the event a reverse battery condition occurs,
the supply current is typically less than 1nA.
Inputs
The LT1782 has two input stages, NPN and PNP (see the
SimplifiedSchematic),resultinginthreedistinctoperating
regions as shown in the Input Bias Current vs Common
Mode typical performance curve.
For input voltages about 0.8V or more below V+, the PNP
input stage is active and the input bias current is typically
–8nA. When the input common mode voltage is within
0.5V of the positive rail, the NPN stage is operating and
the input bias current is typically 15nA. Increases in tem-
peraturewillcausethevoltageatwhichoperationswitches
from the PNP input stage to the NPN input stage to move
towards V+. The input offset voltage of the NPN stage is
untrimmed and is typically 1.8mV.
A Schottky diode in the collector of the input NPN tran-
sistors, along with special geometries for these NPN
transistors, allows the LT1782 to operate with either or
both of its inputs above V+. At about 0.3V above V+, the
NPN input transistor is fully saturated and the input bias
current is typically 4A at room temperature. The input
offset voltage is typically 1.8mV when operating above
V+. The LT1782 will operate with its inputs 18V above
V– regardless of V+.
The inputs are protected against excursions as much as
10V below V– by an internal 6k resistor in series with each
input and a diode from the input to the negative supply.
The input stage of the LT1782 incorporates phase reversal
protection to prevent the output from phase reversing for
inputs up to 9V below V–. There are no clamping diodes
between the inputs and the maximum differential input
voltage is 18V.
Output
The output of the LT1782 can swing to within 60mV of the
positive rail with no load and within 3mV of the negative
rail with no load. When monitoring voltages within 60mV
of the positive rail or within 3mV of the negative rail, gain
should be taken to keep the output from clipping. The
LT1782 can sink and source over 30mA at ±5V supplies,
SHUTDOWN PIN VOLTAGE (V)
0
0.5
1
1.5
2
2.5
SUPPLY
CURRENT
(A)
1782 G28
50
40
30
20
10
0
TA = 25°C
TA = –55°C
TA = 125°C
VS = 5V, 0V
VS = ±5V
AV = 1
CL = 15pF
1782 G29
VS = ±5V
AV = 1
CL = 15pF
1782 G30
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