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| 型號： | LT1970CFE |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 25/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP ADJ CURR LIMIT 20-TSSOP |
| 標準包裝： | 74 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 轉換速率： | 1.6 V/µs |
| 增益帶寬積： | 3.6MHz |
| 電流 - 輸入偏壓： | 160nA |
| 電壓 - 輸入偏移： | 200µV |
| 電流 - 電源： | 7mA |
| 電流 - 輸出 / 通道： | 800mA |
| 電壓 - 電源，單路/雙路(±)： | 5 V ~ 36 V，±2.5 V ~ 18 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬）裸露焊盤 |
| 供應商設備封裝： | 20-TSSOP-EP |
| 包裝： | 管件 |
LT1970
8
1970fc
PIN FUNCTIONS
VEE (Pins 1, 10, 11, 20, Package Base): Minus Supply
Voltage. VEE connects to the substrate of the integrated
circuit die, and therefore must always be the most negative
voltage applied to the part. Decouple VEE to ground with
a low ESR capacitor. VEE may be a negative voltage or it
may equal ground potential. Any or all of the VEE pins may
be used. Unused VEE pins must remain open.
V– (Pin 2):
Output Stage Negative Supply. V– may equal
VEE or may be smaller in magnitude. Only output stage
current ows out of V–, all other current ows out of VEE.
V– may be used to drive the base/gate of an external power
device to boost the amplier’s output current to levels above
the rated 500mA of the on-chip output devices. Unless
used to drive boost transistors, V– should be decoupled
to ground with a low ESR capacitor.
OUT (Pin 3): Amplier Output. The OUT pin provides the
force function as part of a Kelvin sensed load connection.
OUT is normally connected directly to an external load cur-
rent sense resistor and the SENSE+ pin. Amplier feedback
is directly connected to the load and the other end of the
current sense resistor. The load connection is also wired
directly to the SENSE– pin to monitor the load current.
The OUT pin is current limited to ±800mA typical. This
current limit protects the output transistor in the event
that connections to the external sense resistor are
opened or shorted which disables the precision current
limit function.
SENSE+ (Pin 4): Positive Current Sense Pin. This lead is
normally connected to the driven end of the external sense
resistor. Sourcing current limit operation is activated when
the voltage VSENSE (VSENSE+ – VSENSE–) equals 1/10 of
the programming control voltage at VCSRC (Pin 13). Sink-
ing current limit operation is activated when the voltage
VSENSE equals –1/10 of the programming control voltage
at VCSNK (Pin 12).
FILTER (Pin 5): Current Sense Filter Pin. This pin is
normally not used and should be left open or shorted to
the SENSE– pin. The FILTER pin can be used to adapt the
response time of the current sense ampliers with a 1nF
to 100nF capacitor connected to the SENSE– input. An
internal 1k resistor sets the lter time constant.
SENSE– (Pin 6): Negative Current Sense Pin. This pin is
normally connected to the load end of the external sense
resistor. Sourcing current limit operation is activated when
the voltage VSENSE (VSENSE+ – VSENSE–) equals 1/10 of
the programming control voltage at VCSRC (Pin 13). Sink-
ing current limit operation is activated when the voltage
VSENSE equals –1/10 of the programming control voltage
at VCSNK (Pin 12).
VCC (Pin 7): Positive Supply Voltage. All circuitry except
the output transistors draw power from VCC. Total sup-
ply voltage from VCC to VEE must be between 3.5V and
36V. VCC must always be greater than or equal to V+. VCC
should always be decoupled to ground with a low ESR
capacitor.
–IN (Pin 8): Inverting Input of Amplier. –IN may be any
voltage from VEE – 0.3V to VEE + 36V. –IN and +IN remain
high impedance at all times to prevent current ow into
the inputs when current limit mode is active. Care must
be taken to insure that –IN or +IN can never go to a volt-
age below VEE – 0.3V even during transient conditions or
damage to the circuit may result. A Schottky diode from
VEE to –IN can provide clamping if other elements in the
circuit can allow –IN to go below VEE.
+IN (Pin 9): Noninverting Input of Amplier. +IN may be any
voltage from VEE – 0.3V to VEE + 36V. –IN and +IN remain
high impedance at all times to prevent current ow into
the inputs when current limit mode is active. Care must
be taken to insure that –IN or +IN can never go to a volt-
age below VEE – 0.3V even during transient conditions or
damage to the circuit may result. A Schottky diode from
VEE to +IN can provide clamping if other elements in the
circuit can allow + IN to go below VEE.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LT1970CFE#PBF | 功能描述:IC OPAMP ADJ CURR LIMIT 20-TSSOP RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標準包裝:2,500 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:- 轉換速率:0.6 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:45nA 電壓 - 輸入偏移:2000µV 電流 - 電源:1.4mA 電流 - 輸出 / 通道:40mA 電壓 - 電源，單路/雙路(±):3 V ~ 32 V，±1.5 V ~ 16 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:14-TSSOP 包裝:帶卷 (TR) 其它名稱:LM324ADTBR2G-NDLM324ADTBR2GOSTR |
| LT1970CFE#PBF | 制造商:Linear Technology 功能描述:OP AMP 500MA CURR LIMIT 20TSSOP |
| LT1970CFE#TR | 功能描述:IC OPAMP ADJ CURR LIMIT 20-TSSOP RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標準包裝:50 系列:- 放大器類型:J-FET 電路數(shù):2 輸出類型:- 轉換速率:3.5 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:30pA 電壓 - 輸入偏移:2000µV 電流 - 電源:200µA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):7 V ~ 36 V，±3.5 V ~ 18 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:8-DIP（0.300"，7.62mm） 供應商設備封裝:8-PDIP 包裝:管件 |
| LT1970CFE#TRPBF | 功能描述:IC OPAMP ADJ CURR LIMIT 20-TSSOP RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標準包裝:50 系列:- 放大器類型:J-FET 電路數(shù):2 輸出類型:- 轉換速率:3.5 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:30pA 電壓 - 輸入偏移:2000µV 電流 - 電源:200µA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):7 V ~ 36 V，±3.5 V ~ 18 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:8-DIP（0.300"，7.62mm） 供應商設備封裝:8-PDIP 包裝:管件 |
| LT1970CFEPBF | 制造商:Linear Technology 功能描述:LT1970 500mA adj CL power TSSOP op amp |
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