參數(shù)資料
型號(hào)： LT2435-1CGN#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 1-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
封裝： 0.150 INCH, LEAD FREE, PLASTIC, SSOP-16
文件頁(yè)數(shù)： 22/40頁(yè)
文件大?。?/td> 458K
代理商： LT2435-1CGN#PBF
LTC2435/LTC2435-1
29
24351fb
APPLICATIO S I FOR ATIO
WU
U
Figure 25. INL vs Differential Input Voltage (VIN = IN+ – IN–)
and Reference Source Resistance (RSOURCE at REF
+ and
REF– for Large CREF Values (CREF ≥ 1μF)
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
When FO = LOW (internal oscillator and 60Hz notch), every
100
Ω of source resistance driving REF+ or REF– translates
into about 0.11ppm additional INL error. For the LTC2435,
when FO = HIGH (internal oscillator and 50Hz notch), every
100
Ω of source resistance driving REF+ or REF– translates
into about 0.092ppm additional INL error; and for the
LTC2435-1 operating with simultaneous 50Hz/60Hz re-
jection, every 100
Ω of source resistance leads to an
additional 0.10ppm of additional INL error. When FO is
driven by an external oscillator with a frequency fEOSC,
every 100
Ω of source resistance driving REF+ or REF–
translates into about 0.73 10–6 fEOSCppm additional INL
error. Figure 25 shows the typical INL error due to the
source resistance driving the REF+ or REF– pins when
large CREF values are used. The effect of the source
resistance on the two reference pins is additive with
respect to this INL error. In general, matching of source
impedance for the REF+ and REF– pins does not help the
gain or the INL error. The user is thus advised to minimize
the combined source impedance driving the REF+ and
REF– pins rather than to try to match it.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
0.5%. Such a specification can also be easily achieved by
an external clock. When relatively stable resistors
(50ppm/
°C) are used for the external source impedance
seen by REF+ and REF–, the expected drift of the dynamic
current gain error will be insignificant (about 1% of its
value over the entire temperature and voltage range). Even
for the most stringent applications a one-time calibration
operation may be sufficient.
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(
±10nA max), results in a small gain error. A 100Ω source
resistance will create a 0.05
μV typical and 0.5μV maxi-
mum full-scale error.
Figure 24. –FS Error vs RSOURCE at REF
+ and REF– (Large CREF)
Figure 23. +FS Error vs RSOURCE at REF+ and REF– (Large CREF)
RSOURCE (Ω)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–
FS
ERROR
VARIATION
(ppm)
2435 F24
0
400
800
1200
1600
2000
VCC = 5V
VREF+ = 5V
VREF– = GND
VIN+ = 1.25V
VIN– = 3.75V
FO = GND
TA = 25°C
CIN = 1μF, 10μF
CIN = 0.01μF
CIN = 0.1μF
RSOURCE (Ω)
100
90
80
70
60
50
40
30
20
10
0
+FS
ERROR
VARIATION
(ppm)
2435 F23
0
400
800
1200
1600
2000
VCC = 5V
VREF+ = 5V
VREF– = GND
VIN+ = 3.75V
VIN– = 1.25V
FO = GND
TA = 25°C
CIN = 1μF, 10μF
CIN = 0.01μF
CIN = 0.1μF
VINDIF/VREFDIF (V)
15
12
9
6
3
0
–3
–6
–9
–12
–15
INL
(ppm
OF
V
REF
)
2435 F25
0
0.1
–0.1
0.2
–0.2
0.3
–0.3
0.4
–0.4
0.5
–0.5
RSOURCE = 10k
RSOURCE = 5k
RSOURCE = 1k
VINCM = 0.5 (IN
+ + IN–) = 2.5V
VCC = 5V
REF+ = 5V
REF– = GND
FO = GND
CREF = 10μF
TA = 25°C
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