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參數(shù)資料
| 型號： | LT3150CGN#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 259K |
| 描述： | IC REG CTRLR SGL POS ADJ 16-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | More Information on LDOs |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 正，可調(diào)式 |
| 輸出數(shù)： | 1 |
| 輸出電壓： | 2.5 V ~ 18.4 V |
| 電流 - 電源： | 12mA |
| 輸入電壓： | 1.5 V ~ 10 V，10 V ~ 20 V |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
10
LT3150
3150f
APPLICATIO S I FOR ATIO
U
U
U
is low enough such that Q1 and Q2 do not saturate, even
when V
IN1
is 1V. When there is no load, FB1 rises slightly
above 1.23V, causing V
C
(the error amplifiers output) to
decrease. Comparator A2s output stays high, keeping
switch Q3 in the off state. As increased output loading
causes the FB1 voltage to decrease, A1s output increases.
Switch current is regulated directly on a cycle-by-cycle
basis by the V
C
node. The flip flop is set at the beginning
of each switch cycle, turning on the switch. When the
summation of a signal representing switch current and a
ramp generator (introduced to avoid subharmonic oscilla-
tions at duty factors greater than 50%) exceeds the V
C
signal, comparator A2 changes state, resetting the flip flop
and turning off the switch. More power is delivered to the
output as switch current is increased. The output voltage,
attenuated by external resistor divider R1 and R2, appears
at the FB1 pin, closing the overall loop. Frequency com-
pensation is provided internally by R
C
and C
C
. Transient
response can be optimized by the addition of a phase lead
capacitor C
PL
in parallel with R1 in applications where
large value or low ESR output capacitors are used.
As the load current is decreased, the switch turns on for a
shorter period each cycle. If the load current is further
decreased, the converter will skip cycles to maintain
output voltage regulation.
The linear regulator controller section of the LT3150 Block
Diagram consists of a simple feedback control loop and
multiple protection functions. Examining the Block Dia-
gram for the LT3150, a start-up circuit provides controlled
start-up, including the precision-trimmed bandgap refer-
ence, and establishes all internal current and voltage
biasing.
Reference voltage accuracy at the FB2 pin is specified as
?.6% at room temperature and as ?% over the full
operating temperature range. This places the LT3150
among a select group of regulators with a very tightly
specified reference voltage tolerance. The 1.21V reference
is tied to the noninverting input of the main error amplifier
in the feedback control loop.
The error amplifier consists of a single high gain g
m
stage
with a transconductance equal to 15 millimhos. The
inverting terminal is brought out as the FB2 pin. The g
m
stage provides differential-to-single ended conversion at
the COMP pin. The output impedance of the g
m
stage is
about 1M& and thus, 84dB of typical DC error amplifier
open-loop gain is realized along with a typical 75MHz
uncompensated unity-gain crossover frequency. Note
that the overall feedback loops DC gain decreases from
the gain provided by the error amplifier by the attenuation
factor in the resistor divider network which sets the DC
output voltage. External access to the high impedance
gain node of the error amplifier permits typical loop
compensation to be accomplished with a series RC + C
network to ground.
A high speed, high current output stage buffers the COMP
node and drives up to 5000pF of effective MOSFET gate
capacitance with almost no change in load transient per-
formance. The output stage delivers up to 50mA peak
when slewing the MOSFET gate in response to load
current transients. The typical output impedance of the
GATE pin is typically 2&. This pushes the pole due to the
error amplifier output impedance and the MOSFET input
capacitance well beyond the loop crossover frequency. If
the capacitance of the MOSFET used is less than 1500pF,
it may be necessary to add a small value series gate
resistor of 2& to 10&. This gate resistor helps damp the
LC resonance created by the MOSFET gates lead induc-
tance and input capacitance. In addition, the pole formed
by this resistance and the MOSFET input capacitance can
be fine tuned.
Because the MOSFET pass transistor is connected as a
source follower, the power path gain is much more predict-
able than designs that employ a discrete PNP transistor as
the pass device. This is due to the significant production
variations encountered with PNP Beta. MOSFETs are also
very high speed devices which enhance the ability to pro-
duce a stable wide bandwidth control loop. An additional
advantage of the follower topology is inherently good line
rejection. Input supply disturbances do not propagate
through to the output. The feedback loop for a regulator
circuit is completed by providing an error signal to the FB2
pin. A resistor divider network senses the output voltage
and sets the regulated DC bias point. In general, the LT3150
regulator feedback loop permits a loop crossover frequency
on the order of 1MHz while maintaining good phase and gain
margins. This unity-gain frequency is a factor of 20 to 30
times the bandwidth of currently implemented regulator
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