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參數(shù)資料
| 型號： | LT3150CGN |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Fast Transient Response, Low Input Voltage, Very Low Dropout Linear Regulator Controller |
| 中文描述： | 0.8 A SWITCHING CONTROLLER, 1900 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大小： | 263K |
| 代理商： | LT3150CGN |
15
LT3150
3150f
APPLICATIOU
Frequency Compensation
Frequency compensation is the most critical step in de-
signing an LT3150 application circuit. Frequency compen-
sation stabilizes the feedback loop under all line, load and
temperature conditions and determines the transient load
step performance.
To start the frequency compensation process, gather the
following application information. Determine the output
voltage, the minimum and maximum output currents, the
transconductance (g
fs
) of the selected MOSFET at the
minimum and maximum output currents and the output
capacitor type (ceramic, tantalum, electrolytic).
Frequency compensation is accomplished with a passive
network tied from the LT3150’s COMP pin to ground. The
LT3150 generally employs a Type-2 frequency compensa-
tion method. The “Type-2” method uses two poles and one
zero. The output capacitor type determines how the zero
in the feedback loop is set. Ceramic capacitors typically
have very low ESR (equivalent series resistance) and
therefore the COMP pin network sets the “zero” location.
Tantalum and electrolytic capacitors typically have suffi-
cient ESR such that the “zero” formed by the ESR and the
capacitance value is used. Using tantalum or electrolytic
capacitors in LT3150 applications is somewhat more
challenging because the user must choose capacitors with
the proper ESR plus capacitance value to place the zero at
the correct spot in the frequency response.
W
U
U
Figure 3. Simplified Block Diagram for Frequency Compensation
–
+
–
+
V
REF
FB2
R
O
1M
R1
R
F1
R
ESR
R
F2
R
G
V
IN
V
OUT
I
LOAD
3150 F03
Q1
C1
C2
COMP
g
m1
= 0.015
C
O
V
REF
V
OUT
R
F2
R
F1
+ R
F2
=
Refer to the simplified LT3150 block diagram shown in
Figure 3 during the frequency compensation discussion
that follows.
Figure 4 illustrates the typical bode plot and the pole/zero
locations with the use of low ESR ceramic output
capacitors.
Figure 5 illustrates the typical bode plot and the pole/zero
locations with the use of tantalum or electrolytic output
capacitors.
In both output capacitor cases, the location of the first
pole, P1, is set by the error amplifier COMP pin’s open-
loop output impedance, R
O
, and compensation capacitor,
C1. The low frequency gain is set by g
m1
R
O
(V
REF
/V
OUT
)
In the case of low ESR ceramic capacitors, R1 in series
with C1 in the COMP pin network sets the zero, Z1. With
tantalum or electrolytic capacitors, the ESR in series with
the output capacitor C
O
sets Z1. Z1’s location establishes
the mid-band gain or “shelf” gain. For a given value of
output capacitance, the “shelf” gain determines the
regulator’s transient response to an output load step,
especially the output voltage’s peak overshoot and under-
shoot. For a given output load current change, a corre-
sponding delta in the MOSFET’s V
GS
occurs. This
V
GS
divided by the “shelf gain” sets how much the FB2 must
change and thus, results in output voltage perturbation.
Higher “shelf” gain results in lower transient response
peak deviations. Higher shelf gain also translates to a
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