參數(shù)資料
型號(hào)： LT3437
廠商： Linear Technology Corporation
英文描述： Panels; For Use With:EUROCARD Subracks RoHS Compliant: Yes
中文描述： 高電壓，200kHz降壓500mA的降壓開關(guān)穩(wěn)壓器以100？的靜態(tài)電流
文件頁(yè)數(shù)： 17/24頁(yè)
文件大小： 523K
代理商： LT3437
LT3437
17
3437f
APPLICATIU
below 2.4V, switching will be disabled. The undervoltage
lockout threshold doesn’t have any hysteresis and is
mainly used to insure that all internal voltages are at the
correct level before switching is enabled. If an undervolt-
age lockout function with hysteresis is needed to limit
input current at low V
IN
to V
OUT
ratios, refer to Figure 7 and
the following:
W
U
U
V
R
V
R
R
( )
3
V
R
I
V
V
V
R
UVLO
SHDN
3
1
SHDN
2
SHDN
SHDN
HYST
OUT
=
+
+
+
=
1
See the Typical Performance Characteristics section for
graphs of SHDN and V
IN
currents verses input voltage.
SYNCHRONIZING
Oscillator synchronization to an external input is achieved
by connecting a TTL logic-compatible square wave with a
duty cycle between
25%
and
75%
to the LT3437 SYNC
pin. The synchronizing range is equal to initial operating
frequency up to
700kHz
. This means that minimum
practical sync frequency is equal to the worst-case high
self-oscillating frequency (
240kHz
), not the typical oper-
ating frequency of
200kHz
. Caution should be used when
synchronizing above
300kHz,
because at higher sync
frequencies the amplitude of the internal slope compen-
sation used to prevent subharmonic switching is re-
duced. This type of subharmonic switching only occurs at
input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insufficient slope compensa-
tion. Application Note 19 has more details on the theory
of slope compensation.
If the FB pin voltage is below 0.9V (power-up or output
short-circuit conditions), the sync function is disabled.
This allows the frequency foldback to operate to avoid
hazardous conditions for the SW pin.
If a synchronization signal or logic-level above 2V is
present at the SYNC pin, Burst Mode operation is disabled.
Burst Mode operation can be enabled or disabled on the
fly. If no synchronization or Burst Mode defeat is required,
this pin should be connected to ground.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency, switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path,
shown in Figure 8, must be kept as short as possible. This
is implemented in the suggested layouts of Figure 9.
Shortening this path will also reduce the parasitic trace
R1 should be chosen to minimize quiescent current during
normal operation by the following equation:
R
V
V
I
IN
SHDN TYP
1
2
1 5
.
=
( )
(
)
–
(
)
Example:
R
A
M
R
M
M
A
M
k
1
12–
1.
(
(
1 3
.
3
5 1 3
1
6 5
.
1
1 3
.
6 49
.
408
=
μ
)
=
=
)
=
(Nearest 1% 412k)
μ
=
.
–
–
(Nearest 1% 6.49M )
R2=
1.3
7–1.3
1.3M
ENABLE
1.3V
3437 F07
5
μ
A
SHDN
R2
2.4V
–
+
SHDN
COMP
–
+
V
COMP
10
V
IN
V
OUT
LT3437
2
R1
R3
Figure 7. Undervoltage Lockout
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