LT3958
12
3958f
APPLICATIONS INFORMATION
Soft-Start
The LT3958 contains several features to limit peak switch
currents and output voltage (VOUT) overshoot during
start-up or recovery from a fault condition. The primary
purpose of these features is to prevent damage to external
components or the load.
High peak switch currents during start-up may occur in
switching regulators. Since VOUT is far from its nal value,
the feedback loop is saturated and the regulator tries to
charge the output capacitor as quickly as possible, resulting
in large peak currents. A large surge current may cause
inductor saturation or power switch failure.
The LT3958 addresses this mechanism with the SS pin.
As shown in Figure 1, the SS pin reduces the power
MOSFET current by pulling down the VC pin through
Q2. In this way the SS allows the output capacitor to
charge gradually toward its nal value while limiting the
start-up peak currents. The typical start-up waveforms
are shown in the Typical Performance Characteristics
section. The inductor current IL slewing rate is limited by
the soft-start function.
Besides start-up (with EN/UVLO), soft-start can also be
triggered by the following faults:
1. INTVCC > 12.8V (typical)
2. INTVCC < 3.55V
3. Thermal lockout
Any of these three faults will cause the LT3958 to stop
switching immediately. The SS pin will be discharged by
Q3. When all faults are cleared and the SS pin has been
discharged below 0.2V, a 10μA current source IS2 starts
charging the SS pin, initiating a soft-start operation.
The soft-start interval is set by the soft-start capacitor
selection according to the equation:
TSS =CSS
1.25V
10A
FBX Frequency Foldback
When VOUT is very low during start-up, or an output short-
circuit on a SEPIC, an inverting, or a yback converter, the
switching regulator must operate at low duty cycles to
maintain the power switch current within the current limit
range, since the inductor current decay rate is very low
during switch off time. The minimum on-time limitation
may prevent the switcher from attaining a sufciently low
duty cycle at the programmed switching frequency. So, the
switch current may keep increasing through each switch
cycle, exceeding the programmed current limit. To prevent
the switch peak currents from exceeding the programmed
value, the LT3958 contains a frequency foldback function
to reduce the switching frequency when the FBX voltage is
low (see the Normalized Switching Frequency vs FBX graph
in the Typical Performance Characteristics section).
During frequency foldback, external clock synchroniza-
tion is disabled to prevent interference with frequency
reducing operation.
Loop Compensation
Loop compensation determines the stability and transient
performance. The LT3958 uses current mode control to
regulate the output which simplies loop compensation.
The optimum values depend on the converter topology, the
component values and the operating conditions (including
the input voltage, load current, etc.). To compensate the
feedback loop of the LT3958, a series resistor-capacitor
network is usually connected from the VC pin to SGND.
Figure 1 shows the typical VC compensation network. For
most applications, the capacitor should be in the range of
470pF to 22nF, and the resistor should be in the range of 5k
to 50k. A small capacitor is often connected in parallel with
the RC compensation network to attenuate the VC voltage
ripple induced from the output voltage ripple through the
internal error amplier. The parallel capacitor usually ranges
in value from 10pF to 100pF. A practical approach to design
the compensation network is to start with one of the circuits
in this data sheet that is similar to your application, and tune
the compensation network to optimize the performance.
Stability should then be checked across all operating condi-
tions, including load current, input voltage and temperature.
Application Note 76 is a good reference.