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參數(shù)資料
| 型號： | LT4220IGN#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 259K |
| 描述： | IC CTLR HOTSWAP DUAL 16-SSOP |
| 標準包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內部開關： | 無 |
| 電源電壓： | 2.7 V ~ 16.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
12
LT4220
4220f
APPLICATIO S I FOR ATIO
U
U
U
Whenever the output voltages reach their final value as
sensed by R9, R10 and R11, R12 and both gate signals are
fully on, the PWRGD pin will go high impedance.
A typical timing sequence is shown in Figure 8 with
tracking enabled. The sequence is as follows:
1) The power pins make contact and the undervoltage
lockout thresholds are exceeded.
2) The ON comparator thresholds are exceeded and the
GATE pins start ramping up. V
OUT
+ follows GATE
+
by
the N-channel FET threshold voltage.
3) GATE
+
is limited by the tracking circuit because V
OUT
lags behind V
OUT
+. When V
OUT
starts ramping, GATE
holds at approximately the threshold voltage of the
N-channel FET due to C2 slew rate control.
4) When the magnitude of V
OUT
catches up with V
OUT
+,
GATE
+
resumes ramping. The slowest V
OUT
will limit
the faster V
OUT
slew rate.
5) GATE
+
internal gate good signal threshold is reached.
6) GATE
internal gate good signal threshold is reached,
enabling the FB output comparators. If both FB com-
parators indicate the output is good, the PWRGD pin
output goes high impedance and is pulled up by an
external pullup resistor.
Power Supply Ramping
For large capacitive loads, the inrush current will be limited
by the V
OUT
+ and V
OUT
slew rate or by the fold-back
current limit. For a desired inrush current that is less than
the fold-back current limit, the feedback networks R6, C1
and R8, C2 can be used to control the V
OUT
slew rate. For
the desired inrush current and typical gate pull-up current,
the feedback network capacitors C1 and C2 can be calcu-
lated as:
C1 = (10礎 " CL1)/I
INRUSH
+ and
(1)
C2 = (10礎 " CL2)/I
INRUSH
(2)
where CL1 and CL2 are the positive and negative output
load capacitance. If the supply-tracking mode is enabled
(TRACK = High), during startup, the output with the
slowest slew rate will also limit the slew rate of the
opposite output (Note: Supply-tracking is also controlled
by the resistive dividers on the FB pins. See Supply
Tracking). Additionally, C1 and C2 should be greater than
5nF to prevent large overshoot in the output voltage for
transient loads with small capacitive loads.
Capacitor C3 and resistor R8 prevent Q2 from momen-
tarily turning on when the power pins first make contact.
Without C3, capacitor C2 and C
GD(Q2)
would hold the gate
of Q2 near ground before the LT4220 could power up and
pull the gate low. The minimum required value of C3 can
be calculated by:
C
V
V
V
C
C
EE
TH
TH
GD Q
3
2 1 2
2
=
+
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
(
) " .
( )
(3)
where V
TH
is the MOSFETs minimum gate threshold and
V
EEMAX
is the maximum negative supply input voltage. If
C2 is not used, the minimum value for C3 should be 10nF
to ensure stability. C2 and C3 must be the same type to
ensure tracking over temperature.
+UVLO
UVLO
1 2 3 4
5
6
V
CC
V
EE
ON
+
ON
GATE
+
V
OUT
+
GATE
V
OUT
PWRGD
4220 F08
Figure 8. Typical Timing Sequence
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