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參數(shù)資料
| 型號： | LT6109IMS-1#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP CURRENT SENSE 10MSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 放大器，比較器，參考 |
| 應(yīng)用： | 電流感測，電源管理 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
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LT6109-1/LT6109-2
20
610912fa
APPLICATIONS INFORMATION
To ensure (R1 + R2) >> R7, R1 should be chosen such
that R1 >> R7 so that VOUTA does not change significantly
when the comparator trips.
R3 should be chosen to allow sufficient VOL and compara-
tor output rise time due to capacitive loading.
R2 can be calculated:
R2
= R1
VDD –390mV
VHYS(EXTRA)
Note that the hysteresis being added, VHYS(EXTRA), is in
addition to the typical 10mV of built-in hysteresis. For very
large values of R2 PCB related leakage may become an
issue. A tee network can be implemented to reduce the
required resistor values.
The approximate total hysteresis is:
VHYS =10mV+R1
VDD–390mV
R2
For example, to achieve IOVER = 900A with 50mV of total
hysteresis, R7 = 442Ω. Choosing R1 = 4.42k, R3 = 10k
and VDD = 5V results in R2 = 513k.
The analog output voltage will also be affected when the
comparator trips due to the current injected into R7 by
the positive feedback. Because of this, it is desirable to
have (R1 + R2) >> R7. The maximum VOUTA error caused
by this can be calculated as:
VOUTA = VDD
R7
R1
+R2+R7
In the previous example, this is an error of 4.3mV at the
output of the amplifier or 43V at the input of the amplifier
assuming a gain of 100.
When using the comparators with their inputs decoupled
from the output of the amplifier they may be driven directly
by a voltage source. It is useful to know the threshold
voltage equations with additional hysteresis. The input
rising edge threshold which causes the output to transi-
tion from high to low is:
VTH(R) = 400mV 1+
R1
R2
The input falling edge threshold which causes the output
to transition from low to high is:
VTH(F) = 390mV 1+
R1
R2
–VDD
R1
R2
Comparator Outputs
The comparator outputs can maintain a logic low level of
150mV while sinking 500A. The outputs can sink higher
currents at elevated VOL levels as shown in the Typical
PerformanceCharacteristics.Loadcurrentsareconducted
to the V– pin. The output off-state voltage may range
between 0V and 60V with respect to V–, regardless of the
supply voltage used. As with any open-drain device, the
outputs may be tied together to implement wire-OR logic
functions. The LT6109-1 can be used as a single-output
window comparator in this way.
EN/RST Pin
The EN/RST pin performs the two functions of resetting
the latch on the comparators as well as shutting down the
LT6109. After powering on the LT6109, the comparators
must be reset in order to guarantee a valid state at their
outputs.
Applying a pulse to the EN/RST pin will reset the compara-
tors from their tripped state as long as the input on the
comparator is below the threshold and hysteresis for an
invertingcomparatororabovethethresholdandhysteresis
for a noninverting comparator. For example, if VINC1 is
pulled higher than 400mV and latches the comparator, a
reset pulse will not reset that comparator unless its input
is held below the threshold by a voltage greater than the
10mVtypicalhysteresis.Thecomparatoroutputstypically
unlatch in 0.5s with 2pF of capacitive load. Increased
capacitive loading will cause increased unlatch time.
Figure 15 shows the reset functionality of the EN/RST
pin. The width of the pulse applied to reset the compara-
tors must be greater than tRPW(MIN) (2s) but less than
tRPW(MAX) (15s). Applying a pulse that is longer than
40s typically (or tying the pin low) will cause the part
to enter shutdown. Once the part has entered shutdown,
the supply current will be reduced to 3A typically and the
amplifier,comparatorsandreferencewillceasetofunction
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