參數(shù)資料
型號: LT6231IDD#PBF
廠商: Linear Technology
文件頁數(shù): 9/24頁
文件大?。?/td> 0K
描述: IC OP AMP DUAL 215MHZ R-R 8-DFN
標準包裝: 121
放大器類型: 通用
電路數(shù): 2
輸出類型: 滿擺幅
轉換速率: 70 V/µs
增益帶寬積: 215MHz
電流 - 輸入偏壓: 5µA
電壓 - 輸入偏移: 75µV
電流 - 電源: 3.3mA
電流 - 輸出 / 通道: 30mA
電壓 - 電源,單路/雙路(±): 3 V ~ 12.6 V,±1.5 V ~ 6.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-WFDFN 裸露焊盤
供應商設備封裝: 8-DFN-EP(3x3)
包裝: 管件
17
623012fc
LT6230/LT6230-10
LT6231/LT6232
applicaTions inForMaTion
Amplifier Characteristics
Figure 1 is a simplified schematic of the LT6230/LT6231/
LT6232, which has a pair of low noise input transistors
Q1 and Q2. A simple current mirror, Q3/Q4, converts the
differential signal to a single-ended output, and these
transistors are degenerated to reduce their contribution
to the overall noise.
Capacitor C1 reduces the unity-cross frequency and im-
proves the frequency stability without degrading the gain
bandwidth of the amplifier. Capacitor CM sets the overall
amplifier gain bandwidth. The differential drive generator
supplies current to transistors Q5 and Q6 that swing the
output from rail-to-rail.
Input Protection
Thereareback-to-backdiodes,D1andD2acrossthe+and
– inputs of these amplifiers to limit the differential input
voltage to ±0.7V. The inputs of the LT6230/LT6231/LT6232
do not have internal resistors in series with the input tran-
sistors. This technique is often used to protect the input
devices from overvoltage that causes excessive current
to flow. The addition of these resistors would significantly
degrade the low noise voltage of these amplifiers. For
instance, a 100Ω resistor in series with each input would
generate 1.8nV/√Hz of noise, and the total amplifier noise
voltage would rise from 1.1nV/√Hz to 2.1nV/√Hz. Once
the input differential voltage exceeds ±0.7V, steady-state
current conducted through the protection diodes should
be limited to ±40mA. This implies 25Ω of protection re-
sistance is necessary per volt of overdrive beyond ±0.7V.
These input diodes are rugged enough to handle transient
currents due to amplifier slew rate overdrive and clipping
without protection resistors.
The photo of Figure 2 shows the output response to an
input overdrive with the amplifier connected as a voltage
follower. With the input signal low, current source I1 satu-
rates and the differential drive generator drives Q6 into
saturation so the output voltage swings all the way to V.
The input can swing positive until transistor Q2 saturates
into current mirror Q3/Q4. When saturation occurs, the
output tries to phase invert, but diode D2 conducts current
from the signal source to the output through the feedback
connection. The output is clamped a diode drop below the
input. In this photo, the input signal generator is limiting
at about 20mA.
ENABLE
DESD6
DESD5
–V
+V
+VIN
–VIN
+V
623012 F01
BIAS
DIFFERENTIAL
DRIVE GENERATOR
VOUT
+V
CM
I1
–V
DESD3
–V
DESD4
+V
DESD1
–V
DESD2
+V
D1
C1
D2
Q5
Q6
Q4
Q2
Q3
Q1
2.5V
0V
–2.5V
500s/DIV
623012 F02
1V
/DIV
Figure 1. Simplified Schematic
Figure 2. VS = ±2.5V, AV = 1 with Large Overdrive
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