參數(shù)資料
型號(hào)： LT6350IMS8#TRPBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO8
封裝： LEAD FREE, PLASTIC, MSOP-8
文件頁(yè)數(shù)： 24/28頁(yè)
文件大?。?/td> 462K
代理商： LT6350IMS8#TRPBF
LT6350
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6350fb
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Inputs are protected by diodes to each supply. Additionallly,
op amp inputs +IN1, –IN1 and +IN2 are protected by back-to-back diodes
across the op amp inputs. If inputs are taken beyond the supplies or if
either op amp’s differential input voltage exceeds 0.7V, the input current
must be limited to less than 20mA.
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted indenitely.
Note 4: The LT6350C/LT6350I are guaranteed functional over the
temperature range of –40°C to 85°C. The LT6350H is guaranteed
functional over the temperature range of –40°C to 125°C.
Note 5: The LT6350C is guaranteed to meet specied performance from
0°C to 70°C. The LT6350C is designed, characterized and expected to
meet specied performance from –40°C to 85°C, but is not tested or
QA sampled at these temperatures. The LT6350I is guaranteed to meet
specied performance from –40°C to 85°C. The LT6350H is guaranteed to
meet specied performance from –40°C to 125°C.
Note 6: VOS2 is measured as the total output common mode voltage offset
(error between output common mode and voltage at V2). VOS2 includes
the combined effects of op amp 2’s voltage offset, IB, IOS and mismatch
between on-chip resistors and the 499Ω external resistor, R1 (See Figure 1).
Note 7: Supply voltage range is guaranteed by the power supply rejection
ratio test.
Note 8: Output balance is calculated from gain error and gain as:
BAL
GAIN
ERR
=
Note 9: DC linearity is measured by measuring the differential output for
each input in the set V+IN1 = 0.5V, 2.5V, 4.5V, and calculating the maximum
deviation from the least squares best t straight line generated from the
three data points.
Note 10: Output voltage swings are measured between the output and
power supply rails.
Note 11: Full- power bandwidth is calculated from the slew rate.
FPBW = SR/2VP.
ELECTRICAL CHARACTERISTICS The l denotes specications that apply over the full specied temperature range,
otherwise specications are at TA = 25°C. Unless noted otherwise, V+ = 5V, V– = 0V, V+IN1 = V2 = Mid-Supply, VSHDN = V+, RL = OPEN, RF =
SHORT, RG = OPEN. VS is dened as (V+ – V–). VOUTCM is dened as (VOUT1 + VOUT2)/2. VOUTDIFF is dened as (VOUT1 – VOUT2). See Figure 1.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
FPBW
Full-Power Bandwidth (Note 11)
VOUTDIFF = 8VP-P
1.6
MHz
CL
Capacitive Load Drive, 20% Overshoot
No Series Output Resistors
56
pF
SR
Differential Slew Rate
OUT1 Rising (OUT2 Falling)
OUT1 Falling (OUT2 Rising)
48
41
V/μs
HD2
HD3
10kHz Distortion
VS = 5V, VOUTDIFF = 4VP-P, RL = 2kΩ
2nd Harmonic
3rd Harmonic
–115
dBc
HD2
HD3
100kHz Distortion
VS = 5V, VOUTDIFF = 4VP-P, RL = 2kΩ
2nd Harmonic
3rd Harmonic
–102
–97
dBc
HD2
HD3
1MHz Distortion
VS = 5V, VOUTDIFF = 4VP-P, RL = 2kΩ
2nd Harmonic
3rd Harmonic
–86
–75
dBc
tS
Settling Time to a 4V Input Step
0.1%
0.01%
0.0015% (±1LSB, 16-Bit, Falling Edge)
200
240
350
ns
tOVDR
Overdrive Recovery Time
+IN1 to V– and V+
200
ns
tON
Turn-On Time
VSHDN = 0V to 5V
400
ns
tOFF
Turn-Off Time
VSHDN = 5V to 0V
400
ns
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