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參數(shù)資料
| 型號： | LT6552CS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP VID DIFF SGL 3.3V 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 應(yīng)用： | 差分 |
| 電路數(shù)： | 1 |
| -3db帶寬： | 75MHz |
| 轉(zhuǎn)換速率： | 600 V/µs |
| 電流 - 電源： | 14mA |
| 電流 - 輸出 / 通道： | 70mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 12.6 V，±1.5 V ~ 6.3 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
LT6552
6
6552f
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Shutdown Pin Current
VSHDN = –4.5V
q
85
250
A
VSHDN = 4.7V
q
310
A
tON
Turn-On Time
VSHDN from – 4.5V to 4.7V
200
ns
tOFF
Turn-Off Time
VSHDN from 4.7V to –4.5V
400
ns
Shutdown Output Leakage Current
VSHDN = –4.5V, V– ≤ VOUT ≤ V+
q
0.25
A
The q denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = ±5V. Figure 2 shows the DC test circuit, VREF = VCM = 0V,
VDIFF = 0V, VSHDN = V
+, unless otherwise noted. RL = RF + RG = 1k. (Note 6)
±5V ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The inputs are protected from ESD with diodes to the supplies.
Note 3: A heat sink may be required to keep the junction temperature
below absolute maximum.
Note 4: The LT6552C/LT6552I are guaranteed functional over the
temperature range of –40
°C to 85°C.
Note 5: The LT6552C is guaranteed to meet specified performance from
0
°C to 70°C and is designed, characterized and expected to meet specified
performance from –40
°C to 85°C, but is not tested or QA sampled at these
temperatures. The LT6552I is guaranteed to meet specified performance
from – 40
°C to 85°C.
Note 6: When RL = 1k is specified, the load resistor is RF + RG, but when
RL = 150 or RL = 75 is specified, then an additional resistor of that
value is added to the output.
Note 7: VOS measured at the output (Pin 6) is the contribution from both
input pairs and is input referred.
Note 8: Minimum supply is guaranteed by the PSRR test.
Note 9: Full power bandwidth is calculated from the slew rate.
FPBW = SR/2
πVp
Note 10: VS = 3.3V, tr and tf limits are guaranteed by correlation to
VS = 5V and ±5V tests.
Figure 1. 3.3V, 5V DC Test Circuit
Figure 2.
±5V DC Test Circuit
REF
–IN
+IN
V–
FB
V+
OUT
SHDN
+
–
+
–
+
–
+
–
VDIFF
VREF
VCM
VSHDN
V+
RG
100
0.1%
RF
900
0.1%
RL
6552 F01
1
F
REF
–IN
+IN
V–
FB
V+
OUT
SHDN
+
–
+
–
+
–
+
–
+
–
VDIFF
VCM
VSHDN
V+
V–
RG
100
0.1%
RF
900
0.1%
RL
6552 F02
1
F
1
F
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