參數(shù)資料
型號(hào)： LT8500IUHH#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 11/24頁(yè)
文件大小： 0K
描述： IC PWM GENERATOR 56-QFN
標(biāo)準(zhǔn)包裝： 2,500
類(lèi)型： PWM 發(fā)生器
PLL： 無(wú)
主要目的： LED 照明
輸入： CMOS，TTL
輸出： CMOS，TTL
電路數(shù)： 1
比率 - 輸入:輸出： 0.075
差分 - 輸入:輸出： 無(wú)/無(wú)
頻率 - 最大： 50MHz
電源電壓： 3 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 56-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 56-QFN-EP（5x9）
包裝： 帶卷 (TR)
LT8500
19
8500f
the user interface. It can therefore be monitored to con-
firm proper communication with the chip. The following
non-diagnostic status information is continually provided
in the status frame: dot correct registers for each channel
(COR[48:1]), Open LED Testing bit (OLT), phase-shift bit
(PHS), correction register disable (CRD) bit. There are
five unused bits, [5:1], in the field associated with each
channel, all of which are always set to logic zero.
Diagnostic Information Flags
The LT8500 features two kinds of diagnostic information
flags: global out-of-sync error (SYC) and 48 individual
open LED flags (NOL[48:1]).
An out-of-sync error occurs when the part sees an LDI
signal unexpectedly, whether before 584 SCKI clocks,
or coinciding with SCKI high. Either of these events can
corrupt the data and the state of the chip. The SYC bit is
available in every status frame to notify the system if an
erroneous LDI was seen since the first rising edge of SCKI
ofthelastframe.AseriesofmultipleLDI’sbetweenframes,
with no SCKI, is not an out-of-sync error. Recovery from
an out-of-sync error may require the user to completely
rewrite the data and state of the chip. The LDI signal resets
the serial interface.
The OPENLED bits, NOL[48:1], are well suited for use
with the LT3595A, and indicate an open circuit has been
detected on at least one of the 48 LED strings driven by
the three LT3595A’s. The part monitors the three LT3595A
wired-OR OPENLED pins that detect open LED strings
for each LT3595A. When one of the LT3595A’s detects
an open LED string, it will pull OPENLED low during
the PWM high time for that LED string. The state of
OPENLED is captured by the LT8500 on the rising edge
of the first SCKI of a new frame (after LDI). Since SCKI
and PWMCK are asynchronous, the detection of an
open LED string by this method is a probability function
dependent on the frame rate and PWM duty cycle. If a
new frame begins when the PWM pin associated with an
open LED string is high, the OPENLED pin will be driven
low and captured in the status register, but if a new frame
begins when the associated PWM pin is low, the OPENLED
pin will be pulled high and the status register will capture
a default high. When a low OPENLED pin is captured,
signaling an open, each of the 48 OPENLED (NOL[48:1])
status flags will be cleared. Upon detecting this condition
in the status frame, or as a polling strategy, the host may
request an LED self test (CMD = 0x5X), where the LT8500
will test each channel to determine which, if any, is open.
The test drives each PWM pin high, one at a time, in
order, for 64 PWMCK cycles each, and captures the cor-
responding value on the OPENLED pin for the associated
PWM channel. These results will overwrite the NOL flags
in the status frame and the open LED test bit (OLT) will
be set in the status frame to indicate that the NOL data in
this status frame is given by channel. In the next frame,
the OLT bit will be cleared and all 48 NOL bits will again
reflect the state of the OPENLED pin.
PCB Layout Guidelines
The following guidelines should be considered when de-
signing printed circuit boards (PCBs) using the LT8500.
These guidelines are more important as clock speeds and
daisy chain sizes increase.
1. Match the line lengths and delays between SDI and
SCKI to each LT8500.
2. Ensure the timing of LDI to each chip meets SCKI to LDI
setup and hold requirements. In a 5-pin topology, SCKI
is delayed by each chip in the daisy chain, so LDI may
need extra delay to match the delayed SCKI down the
chain. See the discussion on topology in the Operation
section.
3. Avoid cross talk between the communication signals
(SDI, SCKI, LDI, SDO, SCKO) and the PWMs. Even
though the PWM’s signals toggle at a slow rate, all of
their rising edges can occur within a few nanoseconds
of each other.
4. Buffer the signals returning to the host if their paths
are long.
5. Highspeedtechniques:standardhighspeedPCBdesign
techniques should be used on high frequency clock and
datalines.Theseincludeshortpathlengths,shieldingof
high speed data cables and traces, minimized parasitic
capacitance, and reducing antennas and reflections.
6. A ceramic bypass capacitor should be placed close to
the VCC pin.
applicaTions inForMaTion
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參數(shù)描述
LT-8501M 制造商:Mencom 功能描述:
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LT8582EDKD#PBF 制造商:Linear Technology 功能描述:DC/DC CONVRTER BOOST INVERTING SEPIC
LT8582EDKD#TRPBF 功能描述:IC REG MULTI CONFIG ADJ 3A 24DFN RoHS:是 類(lèi)別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 開(kāi)關(guān)穩(wěn)壓器 系列:- 設(shè)計(jì)資源:Design Support Tool 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:升壓（升壓） 輸出類(lèi)型:固定 輸出數(shù):1 輸出電壓:3V 輸入電壓:0.75 V ~ 2 V PWM 型:- 頻率 - 開(kāi)關(guān):- 電流 - 輸出:100mA 同步整流器:是 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:SOT-23-5 細(xì)型，TSOT-23-5 包裝:剪切帶 (CT) 供應(yīng)商設(shè)備封裝:TSOT-23-5 其它名稱(chēng):AS1323-BTTT-30CT
LT8582IDKD#PBF 功能描述:IC REG MULTI CONFIG ADJ 3A 24DFN RoHS:是 類(lèi)別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 開(kāi)關(guān)穩(wěn)壓器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:降壓（降壓） 輸出類(lèi)型:固定 輸出數(shù):1 輸出電壓:1.2V 輸入電壓:2.05 V ~ 6 V PWM 型:電壓模式 頻率 - 開(kāi)關(guān):2MHz 電流 - 輸出:500mA 同步整流器:是 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:6-UFDFN 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:6-SON（1.45x1） 產(chǎn)品目錄頁(yè)面:1032 (CN2011-ZH PDF) 其它名稱(chēng):296-25628-2
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