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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | LTC1063CSW#TR |
| 寤犲晢锛� | Linear Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 15/16闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FILTER LP 5TH ORDER 16-SOIC |
| 妯欐簴鍖呰锛� | 1,000 |
| 婵炬尝鍣ㄩ鍨嬶細 | 宸寸壒娌冩柉锛屼綆閫氶枊闂�(gu膩n)闆诲鍣� |
| 闋荤巼 - 鎴鎴栦腑蹇冿細 | 50kHz |
| 婵炬尝鍣ㄦ暩(sh霉)锛� | 1 |
| 婵炬尝鍣ㄩ殠鏁�(sh霉)锛� | 5th |
| 闆绘簮闆诲锛� | ±2.37 V ~ 8 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 16-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 渚涙噳鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 16-SOIC |
| 鍖呰锛� | 甯跺嵎 (TR) |
LTC1063
8
1063fa
V鈥�
50k
V+
0.1
F
VOUT
1063 TC01
0.1
F
CLOCK IN
鈥�
+
LT1022
20pF
VIN
50k
8
7
6
5
1
2
3
4
LTC1063
CLOCK FREQUENCY (MHz)
1
MAXIMUM
LOAD
CAPACITANCE
(pF
)
200
180
160
140
120
100
80
60
40
20
0
310
1063 F02
24
5
6 78 9
VS = 卤2.5V
VS = 卤5V
VS = 卤7.5V
TA = 25掳C
Output Pin (Pin 7, N Package)
Pin 7 is the filter output. This pin can typically source over
20mA and sink 2mA. Pin 7 should not drive long coax
cables, otherwise the filter鈥檚 total harmonic distortion will
degrade.
Clock Input Pin (Pin 5, N Package)
An external clock when applied to pin 5 tunes the filter
cutoff frequency. The clock-to-cutoff frequency ratio is
100:1. The high (VHIGH) and low (VLOW) clock logic
threshold levels are illustrated in Table 2. Square wave
clocks with duty cycles between 30% and 50% are strongly
recommended. Sinewave clocks are not recommended.
Clock Output Pin (Pin 4, N Package)
Any external clock applied to the clock input pin appears
at the clock output pin. The duty cycle of the clock output
equals the duty cycle of the external clock applied to the
clock input pin. The clock output pin swings to the power
supply rails. When the LTC1063 is used in a self-clocking
mode, the clock of the internal oscillator appears at the
clock output pin with a 30% duty cycle. The clock output
pin can be used to drive other LTC1063s or other ICs. The
maximum capacitance, CL(MAX), the clock output pin can
drive is illustrated in Figure 2.
Table 2. Clock Pin Threshold Levels
POWER SUPPLY
VHIGH
VLOW
VS = 卤2.5V
1.5V
0.5V
VS = 卤5V
3V
1V
VS = 卤7.5V
4.5V
1.5V
VS = 卤8V
4.8V
1.6V
VS = 5V, 0V
4V
3V
VS = 12, 0V
9.6V
7.2V
VS =15V, 0V
12V
9V
Figure 3. Test Circuit for THD
Figure 2. Maximum Load Capacitance at the Clock Output Pin
TEST CIRCUIT
PI FU CTIO S
UU
U
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| LTC1063CSW | IC FILTR 5TH ORDER LOWPASS16SOIC |
| LTC1065CSW | IC FILTR 5TH ORDR LOWPASS 16SOIC |
| LTC1569CS8-6#TRPBF | IC FILTER 10TH ORDR LOWPASS8SOIC |
| VE-2VY-IX-F3 | CONVERTER MOD DC/DC 3.3V 49.5W |
| LTC1569CS8-6#TR | IC FILTER LP 10TH ORD LIN 8SOIC |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
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| LTC1064 | 鍒堕€犲晢:LINER 鍒堕€犲晢鍏ㄧū:Linear Technology 鍔熻兘鎻忚堪:Low Noise, Fast, Quad Universal Filter Building Block |
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| LTC1064-1_09 | 鍒堕€犲晢:LINER 鍒堕€犲晢鍏ㄧū:Linear Technology 鍔熻兘鎻忚堪:Low Noise, 8th Order, Clock Sweepable Elliptic Lowpass Filter |
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