- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗11025 > LTC1068-25IG (Linear Technology)IC FILTR BUILDNG BLK QUAD 28SSOP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | LTC1068-25IG |
| 寤犲晢锛� | Linear Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 27/30闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FILTR BUILDNG BLK QUAD 28SSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 47 |
| 婵炬尝鍣ㄩ鍨嬶細 | 閫氱敤闁嬮棞(gu膩n)闆诲鍣� |
| 闋荤巼 - 鎴鎴栦腑蹇冿細 | 200kHz |
| 婵炬尝鍣ㄦ暩(sh霉)锛� | 4 |
| 婵炬尝鍣ㄩ殠鏁�(sh霉)锛� | 8th |
| 闆绘簮闆诲锛� | 3.14 V ~ 11 V锛�±3.14 V ~ 5.5 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 28-SSOP锛�0.209"锛�5.30mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 28-SSOP |
| 鍖呰锛� | 绠′欢 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�鐣�(d膩ng)鍓嶇27闋�绗�28闋�绗�29闋�绗�30闋�
LTC1068 Series
6
1068fc
ELECTRICAL CHARACTERISTICS LTC1068-25 (Internal Op Amps). The
l
denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at VS = 卤5V, TA = 25掳V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Supply Voltage Range
3.14
卤5.5
V
Voltage Swings
VS = 3.14V, RL = 5k (Note 2)
VS = 4.75V, RL = 5k (Note 3)
VS = 卤5V, RL = 5k
l
1.2
2.6
卤3.4
1.6
3.4
卤4.1
VP-P
V
Output Short-Circuit Current (Source/Sink)
VS = 卤4.75V
VS = 卤5V
17/6
20/15
mA
DC Open-Loop Gain
RL = 5k
85
dB
GBW Product
VS = 卤5V
6
MHz
Slew Rate
VS = 卤5V
10
V/s
Analog Ground Voltage (Note 4)
VS = 5V, Voltage at AGND
2.5V 卤2%
V
LTC1068-25 (Complete Filter) VS = 卤5V, TA = 25掳V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Clock-to-Center Frequency Ratio (Note 5)
VS = 4.75V, fCLK = 500kHz, Mode 1 (Note 3),
fO = 20kHz, Q = 5, VIN = 0.5VRMS,
R1 = R3 = 49.9k, R2 = 10k
l
25 卤0.3
25 卤0.8
25 卤0.9
%
VS = 卤5V, fCLK = 1MHz, Mode 1,
fO = 40kHz, Q = 5, VIN = 1VRMS,
R1 = R3 = 49.9k, R2 = 10k
l
25 卤0.3
25 卤0.8
25 卤0.9
%
Clock-to-Center Frequency Ratio,
Side-to-Side Matching (Note 5)
VS = 4.75V, fCLK = 500kHz, Q = 5 (Note 3)
VS = 卤5V, fCLK = 1MHz, Q = 5
l
卤0.25
卤0.9
%
Q Accuracy (Note 5)
VS = 4.75V, fCLK = 500kHz, Q = 5 (Note 3)
VS = 卤5V, fCLK = 1MHz, Q = 5
l
卤1
卤3
%
fO Temperature Coefficient
卤1
ppm/掳C
Q Temperature Coefficient
卤5
ppm/掳C
DC Offset Voltage (Note 5)
(See Table 1)
VS = 卤5V, fCLK = 1MHz, VOS1
(DC Offset of Input Inverter)
l
0
卤15
mV
VS = 卤5V, fCLK = 1MHz, VOS2
(DC Offset of First Integrator)
l
鈥�2
卤25
mV
VS = 卤5V, fCLK = 1MHz, VOS3
(DC Offset of Second Integrator)
l
鈥�5
卤40
mV
Clock Feedthrough
VS = 卤5V, fCLK = 1MHz
0.25
mVRMS
Max Clock Frequency (Note 6)
VS = 卤5V, Q 鈮� 1.6, Mode 1
5.6
MHz
Power Supply Current
VS = 3.14V, fCLK = 1MHz (Note 2)
VS = 4.75V, fCLK = 1MHz (Note 3)
VS = 卤5V, fCLK = 1MHz
l
3.5
6.5
9.5
8
11
15
mA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Production testing for single 3.14V supply is achieved by using
the equivalent dual supplies of 卤1.57V.
Note 3: Production testing for single 4.75V supply is achieved by
using the equivalent dual supplies of 卤2.375V.
Note 4: Pin 7 (AGND) is the internal analog ground of the device. For
single supply applications this pin should be bypassed with a 1F
capacitor. The biasing voltage of AGND is set with an internal resistive
divider from Pin 8 to Pin 23 (see Block Diagram).
Note 5: Side D is guaranteed by design.
Note 6: See Typical Performance Characteristics.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| VI-J6X-IW-B1 | CONVERTER MOD DC/DC 5.2V 100W |
| VE-B1Z-IW-F4 | CONVERTER MOD DC/DC 2V 40W |
| LTC1569IS8-7#TR | IC FILTER LP 10TH ORD LIN 8SOIC |
| VE-B1Z-IW-F1 | CONVERTER MOD DC/DC 2V 40W |
| VI-J6W-IW-B1 | CONVERTER MOD DC/DC 5.5V 100W |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| LTC1068-25IG#PBF | 鍔熻兘鎻忚堪:IC FILTR BUILDNG BLK QUAD 28SSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鎺ュ彛 - 婵炬尝鍣� - 鏈夋簮 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:1,000 绯诲垪:- 婵炬尝鍣ㄩ鍨�:閫ｇ簩(x霉)鏅�(sh铆)闁擄紝甯堕€氫綆閫� 闋荤巼 - 鎴鎴栦腑蹇�:150kHz 婵炬尝鍣ㄦ暩(sh霉):4 婵炬尝鍣ㄩ殠鏁�(sh霉):8th 闆绘簮闆诲:4.74 V ~ 11 V锛�±2.37 V ~ 5.5 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-SOIC W 鍖呰:甯跺嵎 (TR) |
| LTC1068-25IG#TR | 鍔熻兘鎻忚堪:IC FILTER BUILDG BLK QUAD 28SSOP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鎺ュ彛 - 婵炬尝鍣� - 鏈夋簮 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:1,000 绯诲垪:- 婵炬尝鍣ㄩ鍨�:閫ｇ簩(x霉)鏅�(sh铆)闁�锛屽付閫氫綆閫� 闋荤巼 - 鎴鎴栦腑蹇�:150kHz 婵炬尝鍣ㄦ暩(sh霉):4 婵炬尝鍣ㄩ殠鏁�(sh霉):8th 闆绘簮闆诲:4.74 V ~ 11 V锛�±2.37 V ~ 5.5 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-SOIC W 鍖呰:甯跺嵎 (TR) |
| LTC1068-25IG#TRPBF | 鍔熻兘鎻忚堪:IC FILTR BUILDNG BLK QUAD 28SSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鎺ュ彛 - 婵炬尝鍣� - 鏈夋簮 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:1,000 绯诲垪:- 婵炬尝鍣ㄩ鍨�:閫ｇ簩(x霉)鏅�(sh铆)闁擄紝甯堕€氫綆閫� 闋荤巼 - 鎴鎴栦腑蹇�:150kHz 婵炬尝鍣ㄦ暩(sh霉):4 婵炬尝鍣ㄩ殠鏁�(sh霉):8th 闆绘簮闆诲:4.74 V ~ 11 V锛�±2.37 V ~ 5.5 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-SOIC W 鍖呰:甯跺嵎 (TR) |
| LTC1068-25IG-PBF | 鍒堕€犲晢:LINER 鍒堕€犲晢鍏ㄧū:Linear Technology 鍔熻兘鎻忚堪:Clock-Tunable, Quad Second Order, Filter Building Blocks |
| LTC1068-50CG | 鍔熻兘鎻忚堪:IC FILTR BUILDNG BLK QUAD 28SSOP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鎺ュ彛 - 婵炬尝鍣� - 鏈夋簮 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:1,000 绯诲垪:- 婵炬尝鍣ㄩ鍨�:閫ｇ簩(x霉)鏅�(sh铆)闁�锛屽付閫氫綆閫� 闋荤巼 - 鎴鎴栦腑蹇�:150kHz 婵炬尝鍣ㄦ暩(sh霉):4 婵炬尝鍣ㄩ殠鏁�(sh霉):8th 闆绘簮闆诲:4.74 V ~ 11 V锛�±2.37 V ~ 5.5 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-SOIC W 鍖呰:甯跺嵎 (TR) |
鐧�(f膩)甯冪穵鎬ラ噰璩�(g貌u)锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�
