參數(shù)資料
型號(hào)： LTC1096AC
廠商： Linear Technology Corporation
元件分類(lèi)： 串行ADC
英文描述： Micropower Sampling 8-Bit Serial I/O A/D Converters
中文描述： 微采樣8位串行I /辦公自動(dòng)化/ D轉(zhuǎn)換器
文件頁(yè)數(shù)： 14/28頁(yè)
文件大?。?/td> 452K
代理商： LTC1096AC
14
LTC1096/LTC1096L
LTC1098/LTC1098L
Data Transfer
The CLK synchronizes the data transfer with each bit being
transmitted on the falling CLK edge and captured on the
rising CLK edge in both transmitting and receiving sys-
tems. The LTC1098(L) first receives input data and then
transmits back the A/D conversion result (half duplex).
Because of the half duplex operation, D
IN
and D
OUT
may be
tied together allowing transmission over just three wires:
CS, CLK and DATA (D
IN
/D
OUT
).
Data transfer is initiated by a falling chip select (CS) signal.
After CS falls the LTC1098(L) looks for a start bit. After the
start bit is received, the 3-bit input word is shifted into the
D
IN
input which configures the LTC1098(L) and starts the
conversion. After one null bit, the result of the conversion
U
S
A
O
PPLICATI
U
U
CLK
CS
t
CYC
POWER
DOWN
t
suCS
t
WAKEUP
D
IN
SGL/
DIFF
MSBF
B0*
B1
B2
B3
B4
B5
B6
B7
NULL
BIT
Hi-Z
D
OUT
t
CONV
t
SMPL
HI-Z
START
ODD/
SIGN
DON'T CARE
MSB-FIRST DATA (MSBF = 0)
MSB-FIRST DATA (MSBF = 1)
LTC1096/98 F02
CLK
CS
t
CYC
POWER
DOWN
t
suCS
t
WAKEUP
D
IN
SGL/
DIFF
MSBF
B0
B1
B2
B3
B4
B5
B6
B7
NULL
BIT
Hi-Z
D
OUT
t
CONV
t
SMPL
HI-Z
START
ODD/
SIGN
DON'T CARE
B7*
B6
B5
B4
B3
B2
B1
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.
(MSB)
(MSB)
Figure 2. LTC1098(L) Operating Sequence Example: Differential Inputs (CH
+
, CH
–
)
D
IN
1
D
IN
2
D
OUT
1
D
OUT
2
CS
SHIFT MUX
ADDRESS IN
1 NULL BIT
SHIFT A/D CONVERSION
RESULT OUT
LTC1096/98 AI01
is output on the D
OUT
line. At the end of the data exchange
CS should be brought high. This resets the LTC1098(L) in
preparation for the next data exchange.
The LTC1096(L) does not require a configuration input
word and has no D
IN
pin. A falling CS initiates data transfer
as shown in the LTC1096(L) operating sequence. After CS
falls, the first CLK pulse enables D
OUT
. After one null bit,
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