參數(shù)資料
型號(hào): LTC1096AIS8#TRPBF
廠(chǎng)商: Linear Technology
文件頁(yè)數(shù): 14/32頁(yè)
文件大?。?/td> 0K
描述: IC ADC 8BIT SERIAL I/O 5V 8SOIC
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 8
采樣率(每秒): 33k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 600µW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
輸入數(shù)目和類(lèi)型: 1 個(gè)差分,單極
LTC1096/LTC1096L
LTC1098/LTC1098L
21
10968fc
APPLICATIONS INFORMATION
Figure 7. LTC1098(L) “+” and “–” Input Settling Windows
(Figure 6) and connect the center point to the MPU input.
It should be noted that to get full shutdown, the CS input
of the LTC1096/LTC1098 must be driven to the VCC volt-
age. This would require adding a level shift circuit to the
CS signal in Figure 6.
Figure 6. Interfacing a 9V Powered LTC1096 to a 5V System
BOARD LAYOUT CONSIDERATIONS
Grounding and Bypassing
The LTC1096(L)/LTC1098(L) should be used with an analog
ground plane and single point grounding techniques. The
GND pin should be tied directly to the ground plane.
The VCC pin should be bypassed to the ground plane with
a 1μF tantalum with leads as short as possible. If power
supply is clean, the LTC1096(L)/LTC1098(L) can also oper-
ate with smaller 0.1μF surface mount or ceramic bypass
capacitors. All analog inputs should be referenced directly
to the single point ground. Digital inputs and outputs should
be shielded from and/or routed away from the reference
and analog circuitry.
SAMPLE-AND-HOLD
Both the LTC1096(L) and the LTC1098(L) provide a built-in
sample-and-hold (S&H) function to acquire signals. The
S&H of the LTC1096(L) acquires input signals from “+”
input relative to “–” input during the tWAKEUP time (see
Figure 1). However, the S&H of the LTC1098(L) can sample
input signals in the single-ended mode or in the differential
inputs during the tSMPL time (see Figure 7).
Single-Ended Inputs
The sample-and-hold of the LTC1098(L) allows conversion
of rapidly varying signals. The input voltage is sampled
during the tSMPL time as shown in Figure 7. The sampling
interval begins as the bit preceding the MSBF bit is shifted
+IN
–IN
GND
VCC
CLK
DOUT
VREF
50k
6V
4.7μF
MPU
(e.g. 8051)
5V
P1.4
P1.3
P1.2
10968 F06
DIFFERENTIAL INPUTS
COMMON MODE RANGE
0V TO 6V
9V
LTC1096
9V
OPTIONAL
LEVEL SHIFT
CS
CLK
DIN
DOUT
"+" INPUT
"–" INPUT
SAMPLE
HOLD
"+" INPUT MUST
SETTLE DURING
THIS TIME
tSMPL
tCONV
CS
SGL/DIFF
START
MSBF
DON'T CARE
1ST BIT TEST "–" INPUT MUST
SETTLE DURING THIS TIME
B7
10968 F07
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