參數(shù)資料
型號: LTC1096LI
廠商: Linear Technology Corporation
英文描述: Dual Precision Single Supply Low-Power Operational Amplifier 8-PDIP -40 to 85
中文描述: 微采樣8位串行I /辦公自動化/ D轉(zhuǎn)換器
文件頁數(shù): 7/28頁
文件大小: 452K
代理商: LTC1096LI
7
LTC1096/LTC1096L
LTC1098/LTC1098L
SYMBOL
t
SMPL
f
SMPL(MAX)
t
CONV
t
dDO
t
dis
t
en
t
hDO
t
f
t
r
C
IN
PARAMETER
Analog Input Sample Time
Maximum Sampling Frequency
Conversion Time
Delay Time, CLK
to D
OUT
Data Valid
Delay Time, CS
to D
OUT
Hi-Z
Delay Time, CLK
to D
OUT
Enable
Time Output Data Remains Valid After CLK
D
OUT
Fall Time
D
OUT
Rise Time
Input Capacitance
CONDITIONS
See Operating Sequence
MIN
TYP
1.5
MAX
UNITS
CLK Cycles
G
16.5
kHz
See Operating Sequence
See Test Circuits (Note 9)
See Test Circuits (Note 9)
See Test Circuits (Note 9)
C
LOAD
= 100pF
See Test Circuits (Note 9)
See Test Circuits (Note 9)
Analog Inputs On Channel
Analog Inputs Off Channel
Digital Input
8
CLK Cycles
G
500
220
160
400
70
50
25
5
5
1000
800
480
ns
ns
ns
ns
ns
ns
pF
pF
pF
G
G
G
250
150
G
LTC1096/LTC1098
V
CC
= 3V, V
REF
= 2.5V, f
CLK
= 250kHz, unless otherwise noted.
LTC1096L/LTC1098L
V
CC
= 2.65V, V
REF
= 2.5V, f
CLK
= 250kHz, unless otherwise noted.
SYMBOL
PARAMETER
t
SMPL
Analog Input Sample Time
f
SMPL(MAX)
Maximum Sampling Frequency
t
CONV
Conversion Time
t
dDO
Delay Time, CLK
to D
OUT
Data Valid
t
dis
Delay Time, CS
to D
OUT
Hi-Z
t
en
Delay Time, CLK
to D
OUT
Enable
t
hDO
Time Output Data Remains Valid After CLK
t
f
D
OUT
Fall Time
t
r
D
OUT
Rise Time
C
IN
Input Capacitance
CONDITIONS
See Operating Sequence
MIN
TYP
1.5
MAX
UNITS
CLK Cycles
G
16.5
kHz
See Operating Sequence
See Test Circuits
See Test Circuits
See Test Circuits
C
LOAD
= 100pF
See Test Circuits
See Test Circuits
Analog Inputs On Channel
Analog Inputs Off Channel
Digital Input
8
CLK Cycles
G
500
220
160
400
70
50
25
5
5
1000
800
480
ns
ns
ns
ns
ns
ns
pF
pF
pF
G
G
G
250
200
G
The
G
denotes specifications which apply over the operating temperature
range.
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All voltage values are with respect to GND.
Note 3:
For the 8-lead PDIP, consult the factory.
Note 4:
Linearity error is specified between the actual and points of the
A/D transfer curve.
Note 5:
Total unadjusted error includes offset, full scale, linearity,
multiplexer and hold step errors.
Note 6:
Two on-chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode drop
below GND or one diode drop above V
CC
. This spec allows 50mV forward
bias of either diode. This means that as long as the reference or analog
input does not exceed the supply voltage by more than 50mV, the output
code will be correct. To achieve an absolute 0V to 5V input voltage range
will therefore require a minimum supply voltage of 4.950V over initial
tolerance, temperature variations and loading. For 5.5V < V
CC
9V,
reference and analog input range cannot exceed 5.55V. If reference and
analog input range are greater than 5.55V, the output code will not be
guaranteed to be correct.
Note 7:
The supply voltage range for the LTC1096L/LTC1098L is from
2.65V to 4V. The supply voltage range for the LTC1096 is from 3V to 9V,
but the supply voltage range for the LTC1098 is only from 3V to 6V.
Note 8:
Channel leakage current is measured after the channel selection.
Note 9:
These specifications are either correlated from 5V specifications or
guaranteed by design.
AC CHARACTERISTICS
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