參數(shù)資料
型號(hào): LTC1096LIS8#TR
廠商: Linear Technology
文件頁數(shù): 8/32頁
文件大?。?/td> 0K
描述: IC ADC 8BIT SERIAL I/O 3V 8SOIC
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 8
采樣率(每秒): 33k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 600µW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)差分,單極
LTC1096/LTC1096L
LTC1098/LTC1098L
16
10968fc
The wake-up time is inherently provided for the LTC1098(L)
with setup time = 1μs (see Figure 2).
Data Transfer
The CLK synchronizes the data transfer with each bit being
transmitted on the falling CLK edge and captured on the
rising CLK edge in both transmitting and receiving sys-
tems. The LTC1098(L) rst receives input data and then
transmits back the A/D conversion result (half duplex).
Because of the half duplex operation, DIN and DOUT may
be tied together allowing transmission over just three
wires: CS, CLK and DATA (DIN/DOUT).
Data transfer is initiated by a falling chip select (CS) signal.
After CS falls the LTC1098(L) looks for a start bit. After the
start bit is received, the 3-bit input word is shifted into the
DIN input which congures the LTC1098(L) and starts the
conversion. After one null bit, the result of the conversion
Figure 1. LTC1096(L) Operating Sequence
is output on the DOUT line. At the end of the data exchange
CS should be brought high. This resets the LTC1098(L) in
preparation for the next data exchange.
The LTC1096(L) does not require a conguration input
word and has no DIN pin. A falling CS initiates data trans-
feras shown in the LTC1096(L) operating sequence. After
CS falls, the rst CLK pulse enables DOUT. After one null
bit, the A/D conversion result is output on the DOUT line.
Bringing CS high resets the LTC1096(L) for the next data
exchange.
CLK
tCYC
CS
B7*
B6
B5
B4
B3
B2
B1
B0
B1
B2
B3
B4
B5
B6
B7
NULL
BIT
Hi-Z
DOUT
10968 F01
POWER
DOWN
Hi-Z
tsuCS
tWAKEUP
tCONV
CLK
CS
tCYC
POWER
DOWN
tWAKEUP
B0
B1
B2
B3
B4
B5
B6
B7
Hi-Z
DOUT
tCONV
HI-Z
tsuCS
NULL
BIT
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.
(MSB)
APPLICATIONS INFORMATION
DIN 1
DIN 2
DOUT 1
DOUT 2
CS
SHIFT MUX
ADDRESS IN
1 NULL BIT
SHIFT A/D CONVERSION
RESULT OUT
10968 AI01
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