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參數(shù)資料
| 型號： | LTC1142 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | OCTAL BUS TRANSCEIVER O.C. 20-SOIC 0 to 70 |
| 中文描述： | 雙通道高效率同步降壓型開關穩(wěn)壓器 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 401K |
| 代理商： | LTC1142 |
9
LTC1142/LTC1142L/LTC1142HV
OPERATIOU
As the load current increases, the output voltage de-
creases slightly. This causes the output of the gain stage
[Pin 27(13)] to increase the current comparator thresh-
old, thus tracking the load current.
The sequence of events for Burst Mode
operation is very
similar to continuous operation with the cycle interrupted
by the voltage comparator. When the output voltage is at
or above the desired regulated value, the P-channel
MOSFET is held off by comparator V and the timing
capacitor continues to discharge below V
TH1
. When the
timing capacitor discharges past V
TH2
, voltage compara-
tor S trips, causing the internal sleep line to go low and the
N-channel MOSFET to turn off.
The circuit now enters sleep mode with both power
MOSFETs turned off. In sleep mode a majority of the
circuitry is turned off, dropping the quiescent current
from 1.6mA to 160
μ
A (for one regulator block). The load
current is now being supplied from the output capacitor.
When the output voltage has dropped by the amount of
Refer to Functional Diagram
hysteresis in comparator V, the P-channel MOSFET is
again turned on and this process repeats.
To avoid the operation of the current loop interfering with
Burst Mode
operation, a built-in offset V
OS
is incorporated
in the gain stage. This prevents the current comparator
threshold from increasing until the output voltage has
dropped below a minimum threshold.
To prevent both the external MOSFETs from ever being
turned on at the same time, feedback is incorporated to
sense the state of the driver output pins. Before the NDrive
output can go high, the PDrive output must also be high.
Likewise, the PDrive output is prevented from going low
while the NDrive output is high.
Using constant off-time architecture, the operating fre-
quency is a function of the input voltage. To minimize the
frequency variation as dropout is approached, the off-time
controller increases the discharge current as V
IN
drops
below V
OUT
+ 1.5V. In dropout the P-channel MOSFET is
turned on continuously (100% duty cycle) providing low
dropout operation with V
OUT
~ V
IN
.
T
he basic LTC1142 application circuit is shown in Figure
1. External component selection is driven by the load
requirement and begins with the selection of R
SENSE
.
Once R
SENSE
is known, C
T
and L can be chosen. Next, the
power MOSFETs and D1 are selected. Finally, C
IN
and
C
OUT
are selected and the loop is compensated. Since the
3.3V and 5V sections in the LTC1142 are identical and
similarly section 1 and section 2 in the LTC1142HV-ADJ/
LTC1142L-ADJ are identical, the process of component
selection is the same for both sections. The circuit shown
in Figure 1 can be configured for operation up to an input
voltage of 20V.
R
SENSE
Selection for Output Current
R
SENSE
is chosen based on the required output current.
The LTC1142 current comparators have a threshold range
which extends from a minimum of 25mV/R
SENSE
to a
maximum of 150mV/R
SENSE
. The current comparator
threshold sets the peak of the inductor ripple current,
APPLICATIU
W
U
U
yielding a maximum output current I
MAX
equal to the peak
value less half the peak-to-peak ripple current. For proper
Burst Mode
operation, I
RIPPLE(P-P)
must be less than or
equal to the minimum current comparator threshold.
Since efficiency generally increases with ripple current,
the maximum allowable ripple current is assumed, i.e.,
I
RIPPLE(P-P)
= 25mV/R
SENSE
(see C
T
and L Selection for
Operating Frequency
section). Solving for R
SENSE
and
allowing a margin for variations in the LTC1142 and
external component values yields:
R
SENSE
MAX
I
=100mV
A graph for Selecting R
SENSE
vs Maximum Output Current
is given in Figure 2.
The load current below which Burst Mode
operation com-
mences, I
BURST
, and the peak short-circuit current I
SC(PK)
,
相關PDF資料 |
PDF描述 |
|---|---|
| LTC1142CG | OCTAL BUS TRANSCEIVER O.C. 20-PDIP 0 to 70 |
| LTC1142L | OCTAL BUS TRANSCEIVER O.C. 20-PDIP 0 to 70 |
| LTC1142L-ADJ | OCTAL BUS TRANSCEIVER O.C. 20-SO 0 to 70 |
| LTC1142-ADJ | RADIATION HARDENED HIGH EFFICIENCY, 5 AMP SWITCHING REGULATORS |
| LTC1142HV-ADJ | RADIATION HARDENED HIGH EFFICIENCY, 5 AMP SWITCHING REGULATORS |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LTC1142_00 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual High Efficiency Synchronous Step-Down Switching Regulators |
| LTC1142-ADJ | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual High Efficiency Synchronous Step-Down Switching Regulators |
| LTC1142CG | 功能描述:IC REG CTRLR BUCK PWM CM 28-SSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:2,000 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:1MHz 占空比:50% 電源電壓:9 V ~ 10 V 降壓:無 升壓:是 回掃:是 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 包裝:帶卷 (TR) |
| LTC1142CG#PBF | 功能描述:IC REG CTRLR BUCK PWM CM 28-SSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:2,000 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:1MHz 占空比:50% 電源電壓:9 V ~ 10 V 降壓:無 升壓:是 回掃:是 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 包裝:帶卷 (TR) |
| LTC1142CG#TR | 功能描述:IC REG CTRLR BUCK PWM CM 28-SSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:4,500 系列:PowerWise® PWM 型:控制器 輸出數(shù):1 頻率 - 最大:1MHz 占空比:95% 電源電壓:2.8 V ~ 5.5 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 125°C 封裝/外殼:6-WDFN 裸露焊盤 包裝:帶卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名稱:LM1771SSDX |
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