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參數(shù)資料
| 型號： | LTC1152IS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP 0-DRFT R-R IN/OUT 8SOIC |
| 標準包裝： | 2,500 |
| 系列： | C-Load™ |
| 放大器類型： | 斷路器（零漂移） |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 0.5 V/µs |
| 增益帶寬積： | 700kHz |
| 電流 - 輸入偏壓： | 10pA |
| 電壓 - 輸入偏移： | 1µV |
| 電流 - 電源： | 2.2mA |
| 電壓 - 電源，單路/雙路(±)： | 2.7 V ~ 14 V，±1.35 V ~ 7 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
7
LTC1152
Compensation/Bandwidth Limiting
The LTC1152 is unity-gain stable with capacitive loads up
to 1000pF. Larger capacitive loads can be driven by
externally compensating the LTC1152. Adding 1000pF
between COMP (pin 5) and OUT (pin 6) allows capacitive
loading of up to 1
F; 0.1F between pins 5 and 6 allows the
LTC1152 to drive infinite capacitive load (Figure 3).
1
2
3
4
8
7
6
5
CC
OUTPUT
*OPTIONAL DIODES TO PREVENT
LATCH-UP WITH CC > 1F
1N4148*
1152 F03
1N4148*
LTC1152
V –
V+
Figure 3. Output Compensation Connection
Large compensation capacitors can also be used to limit
the bandwidth of the LTC1152. With 0.1
F from pin 5 to
pin 6, the LTC1152’s gain-bandwidth product is reduced
from 700kHz to around 200Hz. Note that compensation
capacitors greater than 1
F can cause latch-up under
severe output fault conditions; this can be prevented by
clamping pin 5 to each supply with standard signal diodes,
as shown in Figure 3.
Shutdown
The LTC1152 includes a shutdown pin (pin 1). When this
pin is at V +, the LTC1152 operates normally. An internal
1
A pull-up keeps the pin high if it is left floating. When pin
1 is pulled low, the part enters shutdown mode; supply
current drops to 1
A, all internal clocking stops and the
output enters a high impedance state. During shutdown
the voltage at the CP pin (pin 8) will drop to 0.5V below V +.
When pin 1 is brought high again, about 10
s will elapse
before the charge pump regains full voltage. During this
time the LTC1152 will operate normally, but the input CMR
may not include V+. Pin 1 is compatible with CMOS logic
running from the same supply as the LTC1152. Addition-
ally, the input trip levels allow ground referenced CMOS
logic signals to interface directly to pin 1 when the LTC1152
is running from
±5V or ±3V supplies. The internal 1A
pull-up also allows pin 1 to interface with open-collector/
open-drain devices or discrete transistors.
The high impedance output in shutdown allows several
LTC1152s to be connected together as a MUX, with their
outputs tied in parallel and the active channel selected by
using the shutdown pins. Deselected (shutdown) chan-
nels will go to high impedance at the outputs, preventing
them from fighting with the active channel. This works
best when the individual LTC1152s are connected in
noninverting feedback configurations to prevent the feed-
back resistors from passing signals through deselected
channels. See the Typical Applications section for a circuit
example.
Zero-Drift Operation
The LTC1152 is a zero-drift op amp. Like other LTC zero-
drift op amps, it features virtually error-free DC perfor-
mance, very little drift over time and temperature, and very
low noise at low frequencies. The internal nulling clock
runs at about 2.3kHz (the charge pump frequency of
4.7MHz divided by 2048) and is synchronized to the
internal charge pump to prevent beat frequencies from
appearing at the output. The self-nulling circuit constantly
corrects the input offset voltage, keeping it typically below
±1V over the entire input common-mode range. This has
the added benefit of providing exceptional CMRR and
PSRR at low frequencies––far better than competing rail-
to-rail op amps.
Because it uses a sampling front end, the LTC1152 will
exhibit aliasing behavior and clock noise at frequencies
near the internal 2.3kHz sampling frequency. The LTC1152
includes an internal anti-aliasing circuit to keep these error
terms to a minimum. As a rule, alias frequencies will be
down by (80dB – ACLG) in most standard amplifier con-
figurations, where ACLG is the closed-loop gain of the
LTC1152 circuit. Clock noise is also dependent on closed-
loop gain; it will generally consist of spikes of about 100
V
in amplitude, input referred. In general, these error terms
are too small to affect most applications. For a more
detailed explanation of zero-drift amplifier behavior, see
the LTC1051/LTC1053 data sheet.
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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