參數資料
型號： LTC1196-2BCS8
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 8-Bit, SO-8, 1MSPS ADCs with Auto-Shutdown Options
中文描述： 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝： PLASTIC, SOIC-8
文件頁數： 14/28頁
文件大小： 452K
代理商： LTC1196-2BCS8
14
LTC1196/LTC1198
U
S
A
OVERVIEW
The LTC1196/LTC1198 are 600ns sampling 8-bit A/D
converters packaged in tiny 8-pin SO packages and oper-
ating on 3V to 6V supplies. The ADCs draw only 10mW
from a 3V supply or 50mW from a 5V supply.
Both the LTC1196 and the LTC1198 contain an 8-bit,
switched-capacitor ADC, a sample-and-hold, and a serial
port (see Block Diagram). The on-chip sample-and-holds
have full-accuracy input bandwidths of 1MHz. Although
they share the same basic design, the LTC1196 and
LTC1198 differ in some respects. The LTC1196 has a
differential input and has an external reference input pin.
It can measure signals floating on a DC common-mode
voltage and can operate with reduced spans below 1V. The
O
PPLICATI
IU
U
LTC1198 has a 2-channel input multiplexer and can con-
vert either channel with respect to ground or the difference
between the two. It also automatically powers down when
not performing conversion, drawing only leakage current.
SERIAL INTERFACE
The LTC1196/LTC1198 will interface via three or four
wires to ASICs, PLDs, microprocessors, DSPs, or shift
registers (see Operating Sequence in Figures 1 and 2). To
run at their fastest conversion rates (600ns), they must be
clocked at 14.4MHz. HC logic families and any high speed
ASIC or PLD will easily interface to the ADCs at that speed
(see Data Transfer and Typical Application sections). Full
speed operation from a 3V supply can still be achieved with
3V ASICs, PLDs or HC logic circuits.
Figure 2. LTC1198 Operating Sequence Example: Differential Inputs (CH1, CH0)
Figure 1. LTC1196 Operating Sequence
1196/98 F02
CLK
CS
POWER
DOWN
D
IN
SGL/
DIFF
DUMMY
B3
B4
B5
B6
B7
NULL BITS
Hi-Z
D
OUT
t
SMPL
(2.5CLKs)
HI-Z
START
ODD/
SIGN
DON’T CARE
B0*
B2
B1
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.
t
suCS
t
CYC
(16 CLKs)
DUMMY
t
dDO
t
CONV
(8.5CLKs)
CLK
CS
B1
B2
B3
B4
B5
B6
B7
NULL
BITS
Hi-Z
D
OUT
1196/98 F01
Hi-Z
t
suCS
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.
B0*
t
CYC
(12 CLKs)
t
dDO
NULL BITS
B0
t
SMPL
t
CONV
(8.5 CLKs)
t
SMPL
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PDF描述
LTC1198 8-Bit, SO-8, 1MSPS ADCs with Auto-Shutdown Options
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