參數(shù)資料
型號(hào)： LTC1197CS8
廠商： Linear Technology
文件頁(yè)數(shù)： 10/28頁(yè)
文件大?。?/td> 0K
描述： IC A/DCONV 10BIT W/SHTDWN 8-SOIC
標(biāo)準(zhǔn)包裝： 100
位數(shù)： 10
采樣率（每秒）： 500k
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 25mW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOIC
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)差分，單極
18
LTC1197/LTC1197L
LTC1199/LTC1199L
conversion result. However, it is critical that the “–” input
voltage settles completely during the first CLK cycle of the
conversion time and be free of noise. Minimizing RSOURCE–
and C2 will improve settling time (see Figure 6). If a large
“–” input source resistance must be used, the time allowed
for settling can be extended by using a slower CLK
frequency.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 5). Again, the “+” and “–” input sampling times
can be extended as described above to accommodate
slower op amps. High speed op amps such as the LT1224,
LT1191, LT1226 or LT1215 can be made to settle well even
with the minimum settling window of 200ns which occurs
at the maximum clock rate of 7.2MHz.
Source Resistance
The analog inputs of the LTC1197/LTC1197L/LTC1199/
LTC1199L look like a 20pF capacitor (CIN) in series with a
200
resistor (RON) as shown in Figure 6. CIN gets
switched between the selected “+” and “–” inputs once
during each conversion cycle. Large external source resis-
tors and capacitors will slow the settling of the inputs. It is
important that the overall RC time constants be short
enough to allow the analog inputs to completely settle
within the allowed time.
RC Input Filtering
It is possible to filter the inputs with an RC network as
shown in Figure 7. For large values of CF (e.g., 1F), the
capacitive input switching currents are averaged into a net
DC current. Therefore, a filter should be chosen with a
small resistor and large capacitor to prevent DC drops
across the resistor. The magnitude of the DC current is
approximately IDC = 20pF(VIN/tCYC) and is roughly pro-
portional to VIN. When running at the minimum cycle time
of 2
s, the input current equals 50A at VIN = 5V. In this
case a filter resistor of 10
will cause 0.1LSB of full-scale
error. If a larger filter resistor must be used, errors can be
eliminated by increasing the cycle time.
Input Leakage Current
Input leakage currents can also create errors if the source
resistance gets too large. For instance, the maximum
input leakage specification of 1
A(at85°C)flowingthrough
a source resistance of 1k will cause a voltage drop of 1mV
or 0.2LSB. This error will be much reduced at lower
temperatures because leakage drops rapidly (see typical
curve of Input Channel Leakage Current vs Temperature).
REFERENCE INPUTS
The voltage on the reference input of the LTC1197/
LTC1197L defines the voltage span of the A/D converter.
The reference input transient capacitive switching cur-
rents are due to the switched-capacitor conversion tech-
nique used in these ADCs (see Figure 8). During each bit
test of the conversion (every CLK cycle), a capacitive
current spike will be generated on the reference pin by the
ADC. These current spikes settle quickly and do not cause
a problem.
Reduced Reference Operation
The minimum reference voltage of the LTC1199 is 4V and
the minimum reference voltage of the LTC1199L is 2.7V
because the VCC supply and reference are internally tied
together. However, the LTC1197/LTC1197L can operate
with reference voltages below 1V.
Figure 7. RC Input Filtering
Figure 8. Reference Input Equivalent Circuit
APPLICATIO S I FOR ATIO
WU
UU
RFILTER
VIN
CF
1197/99 F07
LTC1199
“
+”
“
–”
IDC
RON
5pF TO 25pF
LTC1197
REF
ROUT
VREF
EVERY CLK CYCLE
5
4
GND
1197/99 F08
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