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參數(shù)資料
| 型號： | LTC1198-2BCS8#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 750KHZ SHUTDWN 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 750k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
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LTC1196/LTC1198
16
119698fb
APPLICATIONS INFORMATION
Dummy Bits
The last two bits of the input word following the MUX ad-
dress are dummy bits. Either bit can be a
logical one or a
logical zero. These two bits allow the ADC 2.5 clocks to
acquire the input signal after the channel selection.
A/D Conversion Result
Both the LTC1196 and the LTC1198 have the A/D conver-
sion result appear on the DOUT line after two null bits (see
the operating sequences in Figures 1 and 2). Data on the
DOUT line is updated on the rising edge of the CLK line.
The DOUT data should also be captured on the rising CLK
edge by the digital systems. Data on the DOUT line remains
valid for a minimum time of thDO (30ns at 5V) to allow the
capture to occur (see Figure 3).
Unipolar Transfer Curve
The LTC1196/LTC1198 are permanently congured for
unipolar only. The input span and code assignment for this
conversion type are shown in the following gures.
CLK
VIH
tdDO
DOUT
1196/98 TC03
VOH
VOL
thDO
Figure 3. Voltage Waveform for DOUT Delay Time, tdDO and thDO
Unipolar Transfer Curve
0V
1LSB
VREF –
2LSB
VREF –
1LSB
VREF
VIN
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0
1196/98 AI04
Unipolar Output Code
OUTPUT CODE
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
INPUT VOLTAGE
VREF – 1LSB
VREF – 2LSB
1LSB
0V
INPUT VOLTAGE
(VREF = 5.000V)
4.9805V
4.9609V
0.0195V
0V
1196/98
AI05
1
2
3
4
CLK
DATA (DIN/DOUT)
START
SGL/DIFF
ODD/SIGN
DUMMY BITS LATCHED
BY LTC1198
LTC1198 CONTROLS DATA LINE AND SENDS
A/D RESULT BACK TO THE DIGITAL SYSTEM
THE DIGITAL SYSTEM CONTROLS DATA LINE
AND SENDS MUX ADDRESS TO LTC1198
THE DIGITAL SYSTEM MUST RELEASE DATA LINE AFTER
5TH RISING CLK AND BEFORE THE 5TH FALLING CLK
LTC1198 TAKES CONTROL OF
DATA LINE ON 5TH FALLING CLK
CS
1196/98 F04
5
DUMMY
Figure 4. LTC1198 Operation with DIN and DOUT Tied Together
Operation with DIN and DOUT Tied Together
The LTC1198 can be operated with DIN and DOUT tied
together. This eliminates one of the lines required to com-
municate to the digital systems. Data is transmitted in both
directions on a single wire. The pin of the digital systems
connected to this data line should be congurable as either
an input or an output. The LTC1198 will take control of
the data line and drive it LOW on the fth falling CLK edge
after the START bit is received (see Figure 4). Therefore,
the port line of the digital systems must be switched to
an input before this happens to avoid a conict.
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| LTC1198-2BCS8-TRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:8-Bit, SO-8, 1Msps ADCs with Auto-Shutdown Options |
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