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參數(shù)資料
| 型號： | LTC1264-7CN#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FILTER 8TH ORDR LOWPASS 14DIP |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 濾波器類型： | 線性相位，低通開關(guān)電容器 |
| 頻率 - 截止或中心： | 200kHz |
| 濾波器數(shù)： | 1 |
| 濾波器階數(shù)： | 8th |
| 電源電壓： | ±2.37 V ~ 8 V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 14-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 14-PDIP |
| 包裝： | 管件 |
LTC1264-7
12647fa
10
NC Pin (1, 5, 8, 13)
Pins 1, 5, 8 and 13 are not connected to any internal circuit
point on the device and should be preferably tied to analog
ground.
Filter Input Pin (2)
The input pin is connected internally through a 50k resis-
tor tied to the inverting input of an op amp.
Analog Ground Pins (3, 5)
The filter performance depends on the quality of the
analog signal ground. For either dual or single supply
operation, an analog ground plane surrounding the pack-
age is recommended. The analog ground plane should be
connected to any digital ground at a single point. For dual
supply operation, pin 3 should be connected to the analog
ground plane. For single supply operation pin 3 should be
biased at 1/2 supply and should be bypassed to the analog
ground plane with at least a 1
F capacitor (Figure 3). For
single 5V operation at the highest fCLK of 2MHz, pin 3
should be biased at 2V. This minimizes passband gain and
phase variations.
Power Supply Pins (4, 12)
The V
+ (pin 4) and the V – (pin 12) should each be
bypassed with a 0.1
F capacitor to an adequate analog
ground. The filter’s power supplies should be isolated
from other digital or high voltage analog supplies. A low
noise linear supply is recommended. Using a switching
power supply will lower the signal-to-noise ratio of the
filter. The supply during power-up should have a slew rate
less than 1V/
s. When V+ is applied before V– and V– is
allowed to go above ground, a signal diode should clamp
V
– to prevent latch-up. Figures 2 and 3 show typical
connections for dual and single supply operation.
Figure 2. Dual Supply Operation for an fCLK/fCUTOFF = 25:1
Figure 3. Single Supply Operation for an fCLK/fCUTOFF = 25:1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VIN
V+
200
V–
VOUT
LTC1264-7
DIGITAL SUPPLY
+
GND
CLOCK SOURCE
1264-7 F02
0.1
F
0.1
F
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VIN
V+
200
VOUT
DIGITAL SUPPLY
+
GND
CLOCK SOURCE
1264-7 F03
+
LTC1264-7
0.1
F
1
F
10k
V+
UU
U
PI FU CTIO S
Filter Output Pins (6, 9)
Pin 9 is the specified output of the filter; it can typically
source 3mA and sink 1mA. Driving coaxial cables or
resistive loads less than 20k will degrade the total har-
monic distortion of the filter. When evaluating the device’s
distortion an output buffer is required. A noninverting
buffer, Figure 4, can be used provided that its input
common-mode range is well within the filter’s output
swing. Pin 6 is an intermediate filter output providing an
unspecified 6th order lowpass filter. Pin 6 should not be
loaded.
1k
1264-7 F04
–
+
LT1220
Figure 4. Buffer for Filter Output
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