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參數(shù)資料
| 型號： | LTC1264CSW#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 0K |
| 描述： | IC FILTER BUILD BLK QUAD 24-SOIC |
| 標準包裝： | 1,000 |
| 濾波器類型： | 通用開關電容器 |
| 頻率 - 截止或中心： | 250kHz |
| 濾波器數(shù)： | 4 |
| 濾波器階數(shù)： | 2nd |
| 電源電壓： | ±2.37 V ~ 8 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 24-SOIC |
| 包裝： | 帶卷 (TR) |
10
LTC1264
1264fb
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Operating Limits
The Typical Maximum Q vs Clock Frequency and Band-
pass Gain Error graphs, under Typical Performance Char-
acteristics, define an upper limit of operating Q for each
LTC1264 2nd order section. These graphs indicate the
power supply, fCLK and Q value conditions under which a
filter implemented with an LTC1264 will remain stable
when operated at temperatures of 85
°C or less. For a 2nd
order section, a bandpass gain error of 3dB or less is
arbitrarily defined as a condition for stability.
When the passband gain error begins to exceed 1dB, the
use of capacitor CC will reduce the gain error (capacitor CC
is connected from the lowpass node to the inverting node
of a 2nd order section). Please refer to Figures 4 through
9. The value of CC can be best determined experimentally,
and as a guide it should be about 5pF for each 1dB of gain
error and not to exceed 15pF. When operating LTC1264
very near the limits defined by the Typical Performance
Characteristics graphs, passband gain variations of 2dB
or more should be expected.
Speed Limitations
To avoid op amp slew rate limiting, the signal amplitude
should be kept below a specified level as shown in Table 2.
Table 2. Maximum VIN vs VS and Clock
VS
MAXIMUM CLOCK
MAXIMUM VIN
±7.5V
4MHz to 5MHz
0.5VRMS fIN ≥ 400kHz
±5V
3MHz to 4MHz
0.5VRMS fIN ≥ 250kHz
Single 5V
1MHz to 2MHz
0.35VRMS fIN ≥ 160kHz
Clock Feedthrough
Clock feedthrough is defined as the RMS value of the clock
frequency and its harmonics that are present at the filter’s
output pins. The clock feedthrough is tested with the
filter’s input grounded and it depends on PC board layout
and on the value of the power supplies. With proper layout
techniques, the typical values of clock feedthrough are
listed under Electrical Characteristics.
Any parasitic switching transients during the rise and fall
edges of the incoming clock are not part of the clock
feedthrough specifications. Switching transients have fre-
quency contents much higher than the applied clock; their
amplitude strongly depends on scope probing techniques
as well as grounding and power supply bypassing. The
clock feedthrough, if bothersome, can be greatly reduced
by adding a simple RC lowpass network at the final filter
output. This RC will completely eliminate any switching
transients.
Wideband Noise
The wideband noise of the filter is the total RMS value of
the device’s noise spectral density and it is used to
determine the operating signal-to-noise ratio. Most of its
frequency contents lie within the filter passband and it
cannot be reduced with post filtering.
The total wideband noise (
VRMS)isnearlyindependentof
the value of the clock. The clock feedthrough specifica-
tions are not part of the wideband noise.
For a specific filter design, the total noise depends on the
Q of each section and the cascade sequence. Table 3
shows typical 2nd order section noise (gain = 1) for Q
values and supplies operating at 25
°C. Noise increases by
20% at the highest operating temperatures.
Table 3. 2nd Order Section Noise (
VRMS) for Modes 1, 1b,
2 or 3 (R2 = R4)
QVS = ±2.5V
VS = ±5V
VS = ±7.5V
140
VRMS
50
60
250
VRMS
60
75
360
VRMS
75
95
475
VRMS
90
115
590
VRMS
110
135
Aliasing
Aliasing is an inherent phenomenon of switched-capacitor
filters and it occurs when the frequency of input signals
approaches the sampling frequency. The input signals
that produce the strongest aliased components have a
frequency, fIN, such as (fSAMPLING – fIN) falls into the
filter’s passband. For the LTC1264 the sampling fre-
quency is twice fCLK. If the input signal spectrum is not
band-limited, aliasing may occur.
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