參數(shù)資料
型號: LTC1272-8ACN
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 12-Bit, 3us, 250kHz Sampling A/D Converter
中文描述: 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP24
封裝: 0.300 INCH, PLASTIC, DIP-24
文件頁數(shù): 15/20頁
文件大?。?/td> 340K
代理商: LTC1272-8ACN
15
LTC1272
U
S
A
O
PPLICATI
U
U
OLD DATA
DB7-DB0
NEW DATA
DB11-DB8
TRACK
HOLD
DATA
BUSY
RD
CS
LTC1272 TA19
t
8
t
1
t
2
t
3
t
CONV
t
11
t
9
t
8
t
9
t
5
t
1
t
4
t
5
t
10
t
3
t
7
t
3
t
7
t
12
t
12
HBEN
t
7
t
4
t
1
t
8
t
9
NEW DATA
DB7-DB0
t
2
t
4
t
5
Figure 17. ROM Mode, Two Byte Read Timing Diagram
Table 5. ROM Mode, Two Byte Read Data Bus Status
Data Outputs
First Read
Second Read
Third Read
D7
DB7
Low
DB7
D6
DB6
Low
DB6
D5
DB5
Low
DB5
D4
DB4
Low
DB4
D3/11
DB3
DB11
DB3
D2/10
DB2
DB10
DB2
D1/9
DB1
DB9
DB1
D0/8
DB0
DB8
DB0
ROM Mode, Two Byte READ
As previously mentioned for a two byte read, only data
outputs D7 . . . D0/8 are used. Conversion is started in the
normal way with a Read operation and the data output
status is the same as the ROM Mode, Parallel Read. See
Figure 17 timing diagram and Table 5 data bus status. Two
more Read operations are required to access the new
conversion result. A delay equal to the LTC1272 conver-
sion time must be allowed between conversion start and
the second data Read operation. The second Read opera-
tion, with HBEN high, disables conversion start and places
the high byte (4 MSBs) on data outputs D3/11 . . . DO18.
A third read operation accesses the low data byte (DB7
. . . DB0) and starts another conversion. The 4 MSB’s
appear on data outputs D11 . . . D8 during all three read
operations above.
Microprocessor Interfacing
The LTC1272 is designed to interface with microproces-
sors as a memory mapped device. The CS and RD control
inputs are common to all peripheral memory interfacing.
The HBEN input serves as a data byte select for 8-bit
processors and is normally connected to the micropro-
cessor address bus.
MC68000 Microprocessor
Figure 18 shows a typical interface for the MC68000. The
LTC1272 is operating in the Slow Memory Mode. Assum-
ing the LTC1272 is located at address C000, then the
following single 16-bit Move instruction both starts a
conversion and reads the conversion result:
Move.W $C000,D0
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