參數(shù)資料
型號(hào): LTC1273AC
廠商: Linear Technology Corporation
元件分類(lèi): 串行ADC
英文描述: 12-Bit, 300ksps Sampling A/D Converters with Reference
中文描述: 12位,300ksps速率與參考采樣A / D轉(zhuǎn)換器
文件頁(yè)數(shù): 17/24頁(yè)
文件大?。?/td> 451K
代理商: LTC1273AC
17
LTC1273
LTC1275/LTC1276
U
S
A
O
PPLICATI
U
U
OLD DATA
DB7-DB0
NEW DATA
DB7-DB0
TRACK
HOLD
DATA
BUSY
RD
CS
LTC1273/75/76 F14
t
8
t
1
t
2
t
3
t
CONV
t
11
t
9
t
8
t
9
t
5
t
1
t
4
t
5
t
10
t
10
t
6
t
7
t
3
t
7
t
12
t
12
HBEN
NEW DATA
DB11-DB8
Figure 14. Slow Memory Mode, Two Byte Read Timing Diagram
Table 3. Slow Memory Mode, Two Byte Read Data Bus Status
Data Outputs
First Read
Second Read
D7
DB7
Low
D6
DB6
Low
D5
DB5
Low
D4
DB4
Low
D3/11
DB3
DB11
D2/10
DB2
DB10
D1/9
DB1
DB9
D0/8
DB0
DB8
that the 4MSBs appear on data output D11...D8 during
both READ operations.
ROM Mode, Parallel Read (HBEN = LOW)
The ROM Mode avoids placing a microprocessor into a
WAIT state. A conversion is started with a READ opera-
tion, and the 12 bits of data from the previous conversion
are available on data outputs D11...D0/8 (see Figure 15
and Table 4). This data may be disregarded if not re-
quired. A second READ operation reads the new data
(DB11...DB0) and starts another conversion. A delay at
least as long as the ADC’s conversion time plus the 600ns
minimum delay between conversions must be allowed
between READ operations.
ROM Mode, Two Byte Read
As previously mentioned for a two byte read, only data
outputs D7...D0/8 are used. Conversion is started in the
normal way with a READ operation and the data output
status is the same as the ROM mode, Parallel Read (see
Figure 16 timing diagram and Table 5 data bus status).
Two more READ operations are required to access the new
conversion result. A delay equal at the ADCs’ conversion
time must be allowed between conversion start and the
third data READ operation. The second READ operation
with HBEN high disables conversion start and places the
high byte (4MSBs) on data outputs D3/11...D0/8. A third
read operation accesses the low data byte (DB7...DB0)
and starts another conversion. The 4MSBs appear on data
outputs D11...D8 during all three read operations.
MICROPROCESSOR INTERFACING
The LTC1273/LTC1275/LTC1276 allow easy interfac-
ing to digital signal processors as well as modern high
speed, 8-bit or 16-bit microprocessors. Here are sev-
eral examples.
相關(guān)PDF資料
PDF描述
LTC1273ACN 12-Bit, 300ksps Sampling A/D Converters with Reference
LTC1273ACS 12-Bit, 300ksps Sampling A/D Converters with Reference
LTC1273 Replaced by TLC2933A : High Performance Phase Locked Loop 14-TSSOP -20 to 75
LTC1273BC 12-Bit, 300ksps Sampling A/D Converters with Reference
LTC1273BCN 12-Bit, 300ksps Sampling A/D Converters with Reference
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