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參數(shù)資料
| 型號： | LTC1273ACN |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 300ksps Sampling A/D Converters with Reference |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 451K |
| 代理商： | LTC1273ACN |
20
LTC1273
LTC1275/LTC1276
U
S
A
This is a two byte read instruction which loads the ADC
data (address B000) into the HL register pair. During the
first read operation, BUSY forces the microprocessor to
WAIT for the LTC1273 conversion. No WAIT states are
inserted during the second read operation when the mi-
croprocessor is reading the high data byte.
O
PPLICATI
U
U
TMS32010 Microcomputer
Figure 20 shows an LTC1273/TMS32010 interface. The
LTC1273 is operating in the ROM Mode.
The LTC1273 is mapped at a port address. The following
I/O instruction starts a conversion and reads the previous
conversion result into data memory.
IN A,PA
(PA = PORT ADDRESS)
When conversion is complete, a second I/O instruction
reads the up-to-date data into memory and starts another
conversion. A delay at least as long as the ADC conversion
time must be allowed between I/O instructions.
MUXing with CD4051
The high input impedance of the LTC1273/LTC1275/
LTC1276 provides an easy, cheap, fast, and accurate way
to multiplex many channels of data through one con-
verter. Figure 21 shows a low cost CD4051 connected to
the LTC1275. The LTC1275’s input draws no DC input
Figure 20. TMS32010 Interface
DATA BUS
LTC1273/75/76 F20
PORT ADDRESS BUS
D0
D11
DEN
PA0
PA2
TMS32010
ADDRESS
DECODE
EN
D0/8
D11
RD
CS
HBEN
LTC1273/75/76
LINEAR CIRCUITRY OMITTED FOR CLARITY
current so it can be accurately driven by the unbuffered
MUX. The CD4520 counter increments the MUX channel
after each sample is taken. Figure 22 shows the acquisi-
tion time of LTC1275 vs the source resistance. For a
500
maximum “on” resistance of the CD4051, the
acquisition time of the ADC is not greatly affected. For
larger source resistances, modest increases in acquisi-
tion time must be allowed.
V
DD
5V
V
SS
V
EE
A
B C
–5V
8 INPUT
CHANNELS
±2.8V
INPUT
VARIES
NO
BUFFER
REQUIRED
D11
D0
CS
RD
BUSY
LTC1275
A
IN
μ
P
OR
DSP
ENABLE
RESET
Q2
Q1
Q0
CD4520
COUNTER
5V
LTC1273/75/76 F21
CD4051
Figure 21. MUXing the LTC1275 with CD4051
SOURCE RESISTANCE (
)
10
2
A
μ
s
3
4
100
1k
10k
LTC1273/75/76 F22
1
0
LTC1275
A
IN
R
SOURCE
V
IN
500
Figure 22. Acqusition Time of LTC1275 vs Source Resistance
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