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參數(shù)資料
| 型號： | LTC1274CS |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 10mW, 100ksps ADCs with 1uA Shutdown |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SO-24 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 411K |
| 代理商： | LTC1274CS |
8
LTC1274/LTC1277
PU
U
RD (Pin 20):
Read Input. This enables the output drivers
when CS is low.
CS (Pin 21):
The Chip Select input must be low for the ADC
to recognize CONVST and RD inputs.
BUSY (Pin 21):
The BUSY output shows the converter
status. It is low when a conversion is in progress. The
rising Busy edge can be used to latch the conversion
result.
V
SS
(Pin 23):
Negative 5V Supply. Negative 5V will select
bipolar operation. Bypass to AGND with 0.1
μ
F ceramic. Tie
this pin to analog ground to select unipolar operation.
V
DD
(Pin 24):
Positive 5V Supply. Bypass to AGND (10
μ
F
tantalum in parallel with 0.1
μ
F ceramic).
U
*The LTC1277 bipolar mode is in offset binary.
LTC1277
A
IN+
(Pin 1):
Positive Analog Input. (A
IN+
– A
IN–
) = 0V to
4.096V, unipolar (V
SS
= 0V) or
±
2.048V, bipolar (V
SS
= –5V).
A
IN–
(Pin 2):
Negative Analog Input. This pin needs to be
free of noise during conversion. For single-ended inputs
tie A
IN–
to analog ground.
V
REF
(Pin 3):
2.42V Reference Output. Bypass to AGND
(10
μ
F tantalum in parallel with 0.1
μ
F ceramic). V
REF
can be
overdriven positive with an external reference voltage.
AGND (Pin 4):
Analog Ground.
REFRDY (Pin 5):
Reference Ready Signal. It goes high
when the reference has settled after SLEEP indicating that
the ADC is ready to sample.
SLEEP (Pin 6):
SLEEP Mode Input. Tie this pin to low to put
the ADC in Sleep mode and save power (REFRDY will go
LOW). The device will draw 1
μ
A in this mode.
NAP (Pin 7):
NAP Mode Input. Pulling this pin low will shut
down all currents in the ADC except the reference. In this
mode the ADC draws 180
μ
A. Wake-up from Nap mode is
about 620ns.
D7 to D4* (Pins 8 to 11):
Three-State Data Outputs.
DGND (Pin 12):
Digital Ground.
D3/11 to D0/8* (Pins 13 to 16):
Three-State Data Outputs.
D11 is the Most Significant Bit.
V
LOGIC
(Pin 17):
5V or 3V Digital Power Supply. This pin
allows a 5V or 3V logic interface with the processor. All
logic outputs (Data Bits, BUSY and REFRDY) will swing
between 0V and V
LOGIC
.
HBEN (Pin 18):
High Byte Enable Input. The four Most
Significant Bits will appear at Pins 13 to 16 when this pin
is high. The LTC1277 uses straight binary for unipolar
mode and offset binary for bipolar mode.
CONVST (Pin 19):
Conversion Start Signal. This active low
signal starts a conversion on its falling edge (to recognize
CONVST, CS has to be low).
RD (Pin 20):
Read Input. This enables the output drivers
when CS is low.
CS (Pin 21):
The Chip Select input must be low for the ADC
to recognize CONVST and RD inputs.
BUSY (Pin 22):
The BUSY output shows the converter
status. It is low when a conversion is in progress.
V
SS
(Pin 23):
Negative 5V Supply. Negative 5V will select
bipolar operation. Bypass to AGND with 0.1
μ
F ceramic. Tie
this pin to analog ground to select unipolar operation.
V
DD
(Pin 24):
5V Positive Supply. Bypass to AGND (10
μ
F
tantalum in parallel with 0.1
μ
F ceramic).
Table 1. LTC1277 Two-Byte Read Data Bus Status
DATA
OUTPUTS
D7
D6
Low Byte
DB7
DB6
High Byte
Low
Low
D5
DB5
Low
D4
DB4
Low
D3/11
DB3
DB11
D2/10
DB2
DB10
D1/9
DB1
DB9
D0/8
DB0
DB8
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