參數(shù)資料
型號(hào)： LTC1274IS
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： Replaced by TLC2933A : High Performance Phase Locked Loop 14-TSSOP -20 to 75
中文描述： 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
封裝： 0.300 INCH, PLASTIC, SO-24
文件頁(yè)數(shù)： 5/20頁(yè)
文件大小： 411K
代理商： LTC1274IS
5
LTC1274/LTC1277
(Note 5) See Figures 13 to 17.
TW U
SYMBOL
t
16
t
17
t
18
PARAMETER
HBEN
↓
to Low Byte Data Valid
HBEN
↑
to RD
↓
Setup Time
RD
↑
to HBEN
↓
Setup Time
CONDITIONS
C
L
= 100pF (LTC1277 Only)
(Note 10) (LTC1277 Only)
(Note 10) (LTC1277 Only)
MIN
TYP
45
MAX
100
UNITS
G
ns
ns
ns
G
10
10
G
The
G
denotes specifications which apply over the full operating
temperature range; all other limits and typicals T
A
= 25
°
C.
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All voltage values are with respect to ground with DGND and
AGND wired together and V
LOGIC
is tied to V
DD
in LTC1277 (unless
otherwise noted).
Note 3:
When these pin voltages are taken below V
SS
(ground for unipolar
mode) or above V
DD
, they will be clamped by internal diodes. This product
can handle input currents greater than 60mA below V
SS
(ground for
unipolar mode) or above V
DD
without latch-up.
Note 4:
When these pin voltages are taken below V
SS
(ground for unipolar
mode), they will be clamped by internal diodes. This product can handle
input currents greater than 60mA below V
SS
(ground for unipolar mode)
without latch-up. These pins are not clamped to V
DD
.
Note 5:
V
DD
= 5V (V
SS
= –5V for bipolar mode), V
LOGIC
= V
DD
(LTC1277),
f
SAMPLE
= 100ksps, t
r
= t
f
= 5ns unless otherwise specified.
Note 6:
Linearity, offset and full-scale specifications apply for unipolar and
bipolar modes.
Note 7:
Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8:
For LTC1274, bipolar offset is the offset voltage measured from
–0.5LSB when the output code flickers between 0000 0000 0000 and
1111 1111 1111. For LTC1277, bipolar offset voltage is measured from
–0.5LSB when the output code flickers between 0111 1111 1111 and
1000 0000 0000.
Note 9:
The AC tests apply to bipolar mode only and the S/(N + D) is 71dB
(typ) for unipolar mode at 100kHz input frequency.
Note 10:
Guaranteed by design, not subject to test.
Note 11:
Recommended operating conditions.
Note 12:
A
IN
must not exceed V
DD
or fall below V
SS
by more than 50mV to
specified accuracy.
Note 13:
The falling CONVST edge starts a conversion. If CONVST returns
high at a bit decision point during the conversion it can create small
errors. For best performance ensure that CONVST returns high either
within 400ns after conversion start (i.e., before the first bit decision) or
after BUSY rises (i.e., after the last bit test). See timing diagrams Modes
1a and 1b (Figures 13, 14).
TYPICAL PERFOR
M
A
CE CHARACTERISTICS
U
Integral Nonlinearity vs
Output Code
OUTPUT CODE
0
–1.00
I
–0.50
0
0.50
1.00
512 1024 1536 2048
LT1274/77 TPC01
2560 3072 3584 4096
f
SAMPLE
= 100kHz
INPUT FREQUENCY (Hz)
10k
E
12
11
10
9
8
7
6
5
4
3
2
1
0
S
74
68
62
56
50
100k
1M
2M
LTC1274/77 TPC03
f
SAMPLE
= 100kHz
NYQUIST
FREQUENCY
OUTPUT CODE
0
–1.00
D
–0.50
0
0.50
1.00
512 1024 1536 2048
LT1274/77 TPC02
2560 3072 3584 4096
f
SAMPLE
= 100kHz
Differential Nonlinearity vs
Output Code
ENOBs and S/(N + D) vs
Input Frequency
相關(guān)PDF資料
PDF描述
LTC1277CS 12-Bit, 10mW, 100ksps ADCs with 1uA Shutdown
LTC1275AC Phase Locked Loop 14-TSSOP -20 to 75
LTC1276BC 12-Bit, 300ksps Sampling A/D Converters with Reference
LTC1276BCN 12-Bit, 300ksps Sampling A/D Converters with Reference
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