參數(shù)資料
型號(hào): LTC1276ACSW#TR
廠商: Linear Technology
文件頁數(shù): 9/24頁
文件大?。?/td> 0K
描述: IC ADC 12BIT SAMPLING REF 24SOIC
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 12
采樣率(每秒): 300k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 75mW
電壓電源: 雙 ±
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)單端,單極;1 個(gè)單端,雙極
17
LTC1273
LTC1275/LTC1276
127356fa
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
OLD DATA
DB7-DB0
NEW DATA
DB7-DB0
TRACK
HOLD
DATA
BUSY
RD
CS
RD
LTC1273/75/76 F14
t8
t1
t2
t 3
t CONV
t11
t9
t8
t9
t5
t1
t4
t5
t10
t6
t7
t3
t7
t12
HBEN
NEW DATA
DB11-DB8
Figure 14. Slow Memory Mode, Two Byte Read Timing Diagram
Table 3. Slow Memory Mode, Two Byte Read Data Bus Status
Data Outputs
D7
D6
D5
D4
D3/11
D2/10
D1/9
D0/8
First Read
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Second Read
Low
DB11
DB10
DB9
DB8
that the 4MSBs appear on data output D11...D8 during
both READ operations.
ROM Mode, Parallel Read (HBEN = LOW)
The ROM Mode avoids placing a microprocessor into a
WAIT state. A conversion is started with a READ opera-
tion, and the 12 bits of data from the previous conversion
are available on data outputs D11...D0/8 (see Figure 15
and Table 4). This data may be disregarded if not re-
quired. A second READ operation reads the new data
(DB11...DB0) and starts another conversion. A delay at
least as long as the ADC’s conversion time plus the 600ns
minimum delay between conversions must be allowed
between READ operations.
ROM Mode, Two Byte Read
As previously mentioned for a two byte read, only data
outputs D7...D0/8 are used. Conversion is started in the
normal way with a READ operation and the data output
status is the same as the ROM mode, Parallel Read (see
Figure 16 timing diagram and Table 5 data bus status).
Two more READ operations are required to access the new
conversion result. A delay equal at the ADCs’ conversion
time must be allowed between conversion start and the
third data READ operation. The second READ operation
with HBEN high disables conversion start and places the
high byte (4MSBs) on data outputs D3/11...D0/8. A third
read operation accesses the low data byte (DB7...DB0)
and starts another conversion. The 4MSBs appear on data
outputs D11...D8 during all three read operations.
MICROPROCESSOR INTERFACING
The LTC1273/LTC1275/LTC1276 allow easy interfac-
ing to digital signal processors as well as modern high
speed, 8-bit or 16-bit microprocessors. Here are sev-
eral examples.
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