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參數(shù)資料
| 型號： | LTC1276BC |
| 廠商： | Linear Technology Corporation |
| 元件分類： | 串行ADC |
| 英文描述： | 12-Bit, 300ksps Sampling A/D Converters with Reference |
| 中文描述： | 12位，300ksps速率與參考采樣A / D轉換器 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 451K |
| 代理商： | LTC1276BC |
5
LTC1273
LTC1275/LTC1276
SYMBOL
t
7
PARAMETER
Bus Relinquish Time
CONDITIONS
MIN
20
20
20
0
0
40
500
600
1000
TYP
30
MAX
75
85
90
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Commercial
Military
G
G
t
8
t
9
t
10
t
11
HBEN to RD Setup Time
HBEN to RD Hold Time
Delay Between RD Operations
Delay Between Conversions
G
G
G
(Note 10)
Commercial
Military
G
G
t
12
Aperture Delay of Sample-and-Hold
25
TW U
LTC1273A/LTC1275A/LTC1276A
LTC1273B/LTC1275B/LTC1276B
See Timing Characteristics Figures (Note 5)
Note 6:
Linearity, offset and full scale specifications apply for unipolar and
bipolar modes.
Note 7:
Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8:
Bipolar offset (LTC1275/LTC1276) is the different voltage
measured from –0.5LSB when the LTC1275/LTC1276 output code flickers
between 0000 0000 0000 and 1111 1111 1111.
Note 9:
Guaranteed by design, not subject to test.
Note 10:
Recommended operating conditions.
Note11:
A
IN
must not exceed V
DD
or fall below V
SS
by more than 50mV for
specified accuracy. Therefore the minimum supply voltage for the
LTC1273 is +4.95V. The minimum supplies for the LTC1275 are +4.75V
and –2.45V and the minimum supplies for the LTC1276 are
±
4.95V.
The
G
indicates specifications which apply over the full operating
temperature range; all other limits and typicals T
A
= 25
°
C.
Note 1:
Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3:
When these pin voltages are taken below V
SS
(ground for
LTC1273) or above V
DD
, they will be clamped by internal diodes. This
product can handle input currents greater than 60mA below V
SS
(ground
for LTC1273) or above V
DD
without latch-up.
Note 4:
When these pin voltages are taken below V
SS
(ground for
LTC1273) they will be clamped by internal diodes. This product can handle
input currents greater than 60mA below V
SS
(ground for LTC1273)
without latch-up. These pins are not clamped to V
DD
.
Note 5:
V
DD
= 5V (V
SS
= –5V for LTC1275/LTC1276), 300kHz at 70
°
C and
250kHz at 125
°
C, t
r
= t
f
= 5ns unless otherwise specified.
TW U
(Note 5)
Slow Memory Mode, Parallel Read Timing Diagram
ROM Mode, Parallel Read Timing Diagram
BUSY
DATA
TRACK
OLD DATA
DB11 TO DB0
NEW DATA
DB11 TO DB0
t
1
HOLD
LTC1273/75/76 TA03
CS
RD
t
5
t
1
t
10
t
11
t
2
t
CONV
t
6
t
3
t
12
t
7
t
1
OLD DATA
DB11 TO DB0
NEW DATA
DB11 TO DB0
DATA
TRACK
HOLD
CS
RD
BUSY
LTC1273/75/76 TA04
t
5
t
1
t
5
t
4
t
2
t
CONV
t
11
t
2
t
CONV
t
3
t
7
t
3
t
12
t
12
t
4
t
7
相關PDF資料 |
PDF描述 |
|---|---|
| LTC1276BCN | 12-Bit, 300ksps Sampling A/D Converters with Reference |
| LTC1273AC | 12-Bit, 300ksps Sampling A/D Converters with Reference |
| LTC1273ACN | 12-Bit, 300ksps Sampling A/D Converters with Reference |
| LTC1273ACS | 12-Bit, 300ksps Sampling A/D Converters with Reference |
| LTC1273 | Replaced by TLC2933A : High Performance Phase Locked Loop 14-TSSOP -20 to 75 |
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