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參數(shù)資料
| 型號： | LTC1277CS |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 10mW, 100ksps ADCs with 1uA Shutdown |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SO-24 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大小： | 411K |
| 代理商： | LTC1277CS |
13
LTC1274/LTC1277
U
S
A
LTC1277 A
IN+
/A
IN–
Input Settling
The input capacitor for the LTC1277 is switched onto the
A
IN+
input during the sample phase. The voltage on the
A
IN+
input must settle completely within the sample
period. At the end of the sample phase the input capacitor
switches to the A
IN–
input and the conversion starts.
During the conversion the A
IN+
input voltage is effec-
tively “held” by the sample-and-hold and will not affect
the conversion result. It is critical that the A
IN–
input
voltage be free of noise and settles completely during the
conversion.
O
PPLICATI
IU
U
3V to keep the input span within the 5V supply in unipolar
mode. In bipolar mode the reference should be driven to
no more than 5V, the positive supply voltage of the chip.
Figure 6 shows an LT1006 op amp driving the Reference
pin. In unipolar mode, the reference can be driven up to
2.95V at which point it will provide a 0V to 5V input span.
For the bipolar mode, the reference can be driven up to 5V
at which point it will provide a
±
4.23V input span. Figure
7 shows a typical reference, the LT1019A-2.5 connected
to the LTC1274. This will provide an improved drift (equal
to the maximum 5ppm/
°
C of the LT1019A-2.5) and a
±
2.115V (bipolar) or 4.231V (unipolar) full scale.
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1274/LTC1277, a printed cir-
cuit board is required. Layout for the printed circuit board
should ensure that digital and analog signal lines are
separated as much as possible. In particular, care should
be taken not to run any digital track alongside an analog
signal track or underneath the ADC. The analog input
should be screened by AGND.
High quality tantalum and ceramic bypass capacitors
should be used at the V
DD
and V
REF
pins as shown in
Internal Reference
The ADCs have an on-chip, temperature compensated,
curvature corrected bandgap reference which is factory
trimmed to 2.42V. It is internally connected to the DAC and
is available at Pin 2 (LTC1274) or Pin 3 (LTC1277) to
provide up to 1mA current to an external load.
For minimum code transition noise the reference output
should be decoupled with a capacitor to filter wideband
noise from the reference (10
μ
F tantalum in parallel with a
0.1
μ
F ceramic).
The V
REF
pin can be driven with a DAC or other means to
provide input span adjustment. The V
REF
pin must be
driven to at least 2.45V to prevent conflict with the internal
reference. The reference should be driven to no more than
Figure 6. Driving the V
REF
with the LT1006 Op Amp
V
REF(OUT)
≥
2.45V
3
INPUT RANGE:
±
0.846V
REF(OUT)
IN BIPOLAR MODE
0 TO 1.69V
REF(OUT)
IN
UNIPOLAR MODE
5V
–
+
LT1006
LTC1274
A
IN
AGND
V
REF
10
μ
F
LTC1274/77 F06
Figure 7. Supplying a 2.5V Reference Voltage
to the LTC1274 with the LT1019A-2.5
3
INPUT RANGE:
±
2.115V (
±
0.846
×
V
REF
)
IN BIPOLAR AND
0V TO 4.231V (1.69V
REF(OUT)
)
IN UNIPOLAR MODE
LTC1274
A
IN
AGND
V
REF
10
μ
F
LTC1274/77 F07
LT1019A-2.5
V
IN
GND
V
OUT
5V
5V
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