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參數(shù)資料
| 型號(hào)： | LTC1282 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 3V 140ksps 12-Bit,Sampling A/D Converter with Reference(3V,140ksps,12位,采樣模數(shù)轉(zhuǎn)換器(帶基準(zhǔn))) |
| 中文描述： | 3V的140ksps 12位，采樣的A / D參考（3V的，140ksps，12位，采樣模數(shù)轉(zhuǎn)換器（帶基準(zhǔn)）轉(zhuǎn)換器） |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 357K |
| 代理商： | LTC1282 |
10
LTC1282
FU
U
W
U
S
A
CONVERSION DETAILS
O
PPLICATI
IU
U
The LTC1282 uses a successive approximation and an
internal sample-and-hold circuitry to convert an analog
signal to a 12-bit parallel or 2-byte output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs. Please refer to the Digital Interface section
for the data format.
Conversion start is controlled by the CS, RD and HBEN
inputs. At the start of conversion the successive approxi-
mation register (SAR) is reset and the three-state data
outputs are enabled. Once a conversion cycle has begun
it cannot be restarted.
During conversion, the internal 12-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the A
IN
input connects to the sample-and-hold
capacitor during the sample phase, and the comparator
offset is nulled by the feedback switch. In this sample
phase, a minimum delay of 1.14
μ
s will provide enough
time for the sample-and-hold capacitor to acquire the
analog signal. During the convert phase, the comparator
feedback switch opens, putting the comparator into the
compare mode. The input switch switches C
SAMPLE
to
ground, injecting the analog input charge to the summing
junction. This input charge is successively compared with
the binary-weighted charges supplied by the capacitive
DAC. Bit decisions are made by the high speed comparator.
At the end of a conversion, the DAC output balances the A
IN
input charge. The SAR contents (a 12-bit data word) which
represent the A
IN
are loaded into the 12-bit latch.
V
DAC
LTC1282 F01
+
–
C
DAC
DAC
SAMPLE
HOLD
C
SAMPLE
S
A
R
12-BIT
LATCH
COMPARATOR
SAMPLE
SI
A
IN
Figure 1. A
IN
Input
C
SAMPLE
CONTROL
LOGIC
INTERNAL
CLOCK
SUCCESSIVE
APPROXIMATION
REGISTER
12
12
OUTPUT
LATCHES
D11
D0/8
BUSY
1.2V
REFERENCE
V
REF(OUT)
DGND
AGND
A
IN
SAMPLE
HOLD
SAMPLE
V
(–3V FOR BIPOLAR MODE,
AGND FOR UNIPOLAR MODE)
V
DD
HBEN
CS
RD
LTC1282 FBD
12-BIT
CAPACITIVE
DAC
COMPARATOR
–
+
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