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參數(shù)資料
| 型號： | LTC1282ACN |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV SAMPLING W/REF 24DIP |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 140k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 24mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極；1 個(gè)單端，雙極 |
18
LTC1282
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Table 4. ROM Mode, Parallel Read Data Bus Status
Data Outputs
D11
D10
D9
D8
D7
D6
D5
D4
D3/11
D2/10
D1/9
D0/8
First Read (Old Data)
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Second Read
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Figure 18. ROM Mode, Parallel Read Timing Diagram (HBEN = LOW)
HOLD
t12
t7
TRACK
DATA
t3
t7
t3
t2
tCONV
t11
t1
t4
t5
t4
t1
t5
t2
t12
OLD DATA
DB11-DB0
NEW DATA
DB11-DB0
BUSY
RD
CS
LTC1282 F18
ROM Mode, Parallel Read (HBEN = LOW)
The ROM Mode avoids placing a microprocessor into a
WAIT state. A conversion is started with a READ operation,
and the 12 bits of data from the previous conversion are
available on data outputs D11...D0/8 (see Figure 18 and
Table 4). This data may be disregarded if not required. A
second READ operation reads the new data (DB11...DB0)
and starts another conversion. A delay at least as long as
the ADC’s conversion time plus the 1.0
s minimum delay
between conversions must be allowed between READ
operations.
ROM Mode, Two Byte Read
As previously mentioned for a two byte read, only data
outputs D7...D0/8 are used. Conversion is started in the
normal way with a READ operation and the data output
status is the same as the ROM mode, Parallel Read (see
Figure 19 timing diagram and Table 5 data bus status).
Two more READ operations are required to access the new
conversion result. A delay equal to the ADC’s conversion
time must be allowed between conversion start and the
second data READ operation. The second READ operation
with HBEN high disables conversion start and places the
high byte (4MSBs) on data outputs D3/11...D0/8. A third
read operation accesses the low data byte (DB7...DB0)
and starts another conversion. The 4MSBs appear on data
outputs D11...D8 during all three read operations.
MICROPROCESSOR INTERFACING
The LTC1282 allows easy interfacing to digital signal
processors as well as modern high speed, 8-bit or 16-
bit microprocessors. Here are several examples.
TMS320C25
Figure 20 shows an interface between the LTC1282 and
the TMS320C25.
The R/W signal of the DSP initiates a conversion and
conversion results are read from the LTC1282 using the
following instruction:
IN
D, PA
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