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參數(shù)資料
| 型號： | LTC1283ACN |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 23/24頁 |
| 文件大小： | 0K |
| 描述： | IC DATA ACQ SYS 10BIT 3V 20-DIP |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 10 b |
| 采樣率（每秒）： | 15k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 電壓電源： | 雙 ± |
| 電源電壓： | ±3.3V，3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-PDIP |
| 包裝： | 管件 |
8
LTC1283
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A
O
PPLICATI
WU
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I FOR ATIO
The LTC1283 is a 3V data acquisition component which
contains the following functional blocks:
1. 10-bit successive approximation capacitive
A/D converter
2. Analog multiplexer (MUX)
3. Sample-and-hold (S&H)
4. Synchronous, full duplex serial interface
5. Control and timing logic
DIGITAL CONSIDERATIONS
1. Serial Interface
The LTC1283 communicates with microprocessors and
other external circuitry via a synchronous, full duplex, 4-
wire serial interface (see Operating Sequence). The shift
clock (SCLK) synchronizes the data transfer with each bit
being transmitted on the falling SCLK edge and captured
on the rising SCLK edge in both transmitting and receiving
systems. The data is transmitted and received simulta-
neously (full duplex).
Data transfer is initiated by a falling chip select (CS) signal.
After the falling CS is recognized, an 8-bit input word is
shifted into the DIN input which configures the LTC1283
for the next conversion. Simultaneously, the result of the
previous conversion is output on the DOUT line. At the end
of the data exchange the requested conversion begins
and CS should be brought high. After tCONV, the conver-
sion is complete and the results will be available on the
next data transfer cycle. As shown below, the result of
a conversion is delayed by one CS cycle from the input
word requesting it.
2. Input Data Word
The LTC1283 8-bit input data word is clocked into the DIN
input on the first eight rising SCLK edges after chip select
is recognized. Further inputs on the DIN pin are then
ignored until the next CS cycle. The eight bits of the input
word are defined as follows:
DIN
DOUT DOUT WORD 0
DIN WORD 1
DATA
TRANSFER
DOUT WORD 2
DIN WORD 3
DOUT WORD 1
DIN WORD 2
DATA
TRANSFER
tCONV
A/D
CONVERSION
tCONV
A/D
CONVERSION
LTC1283 AI02
Operating Sequence
(Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 10-Bit Word Length)
SGL/
DIFF
SELECT
1
SELECT
0
UNI
MSBF
WL1
MUX ADDRESS
MSB-FIRST/
LSB-FIRST
UNIPOLAR/
BIPOLAR
WORD
LENGTH
LTC1283 AI03
ODD/
SIGN
WL0
DATA INPUT (DIN) WORD:
1
2
3
45
67
8
9
10
B9
(SB)
B8
B7
B6
B5
B4
B3
B2
B1
B0
SCLK
DIN
DOUT
CS
LTC1283 AI01
DIFF
ODD/
SIGN
tCONV
tSMPL
tCYC
DON’T CARE
SEL
1
SEL
0
UNI
MSBF
WL1
WL0
SHIFT CONFIGURATION
WORD IN
SHIFT A/D RESULT OUT AND
NEW CONFIGURATION WORD IN
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