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參數(shù)資料
| 型號： | LTC1283CN |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 3V Single Chip 10-Bit Data Acquisition System |
| 中文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大小： | 452K |
| 代理商： | LTC1283CN |
14
LTC1283
U
S
A
O
PPLICATI
IU
U
CS
SCLK
D
IN
D
OUT
G1
SK
SO
SI
ANALOG
INPUTS
LTC1283
COP820C
LTC1283 AI11
Motorola SPI (MC68HC05C4, MC68HC11)
The MC68HC05C4 and MC68HC11 transfer data MSB-
first and in 8-bit increments. Programming the LTC1283
for MSB-first format and 16-bit word length allows the 10-
bit data output to be received by the MPU as two 8-bit
bytes with the final 6 unused bits filled with zeroes by the
LTC1283.
B9
B8
B7
B6
B5
B4
B3
B2
MSB*
LSB
*B9 is MSB in unipolar or sign bit in bipolar
BYTE 1
LTC1283 AI14
B1
B0
0
0
0
0
0
0
BYTE 2
LOCATION A
LOCATION A + 1
MNEMONIC
BCLR n
LDA
STA
↑
NOP
↓
LDA
LDA
COMMENTS
C0 IS CLEARED (CS GOES LOW)
LOAD D
IN
FOR LTC1283 INTO ACC
LOAD D
IN
FROM ACC TO SPI DATA REG. START SCK
8 NOPs FOR TIMING
LOAD CONTENTS OF SPI STATUS REG. INTO ACC
LOAD LTC1283 D
OUT
FROM SPI DATA REG.
INTO ACC (BYTE 1)
LOAD LTC1283 D
OUT
INTO RAM (LOCATION A)
STA
MNEMONIC
STA
↑
NOP
↓
BSET n
LDA
LDA
COMMENTS
START NEXT SPI CYCLE
6 NOPs FOR TIMING
CO IS SET (CS GOES HIGH)
LOAD CONTENTS OF SPI STATUS REG. INTO ACC
LOAD LTC1283 D
OUT
FROM SPI DATA REG.
INT ACC (BYTE 2)
LOAD LTC1283 INTO RAM (LOCATION A +1)
STA
Hardware and Software Interface to Motorola MC68HC05C4 and
MC68HC11 Processors
D
OUT
from LTC1283 stored in MC68HC05C4 or MC68HC11 RAM
9
8
7
6
5
4
3
2
MSB*
LSB
*B9 is MSB in unipolar or sign bit in bipolar
BYTE 1
LTC1283 AI12
1
0
X
X
X
X
X
X
BYTE 2
Hardware and Software Interface to National Semiconductor
COP820C Processor
D
OUT
from LTC1283 stored in COP820C RAM
MNEMONIC
LD (F0)
←
0D
LD (D5)
←
32
LD (EE)
←
8
LD (B)
←
D4
LD (A)
←
(F0)
RBIT 1
X (A)
←→
(E9)
LD (B)
←
EF
SBIT 2
↑
NOP
↓
COMMENTS
LOAD 0D INTO F0 (D
IN
)
CONFIGURE PORT G
CONFIGURE CONTROL REG.
PORT G DATA REG. INTO B
LOAD D
IN
INTO ACC
G1 RESET (CS GOES LOW)
LOAD D
IN
INTO SHIFT REG.
LOAD PSW REG. ADDR IN B
TRANSFER BEGINS
15 NOPs FOR TIMING
MNEMONIC
X(A)
←→
(E9)
SBIT 2
X (A)
←→
(F3)
RBIT 2
LD (B)
←
D4
SBIT 1
X (A)
←→
(E9)
RC
RRCA
RRCA
RRCA
X (A)
←→
(F4)
COMMENTS
LOAD D
OUT
INTO ACC
TRANSFER CONTINUES
LOAD D
OUT
IN ADDR F3
STOP TRANSFER
PUT PORT G ADDR IN B
G1 SET (CS GOES HIGH)
LOAD D
OUT
INTO ACC
CLEAR CARRY
SHIFT RIGHT THRU CARRY
SHIFT RIGHT THRU CARRY
SHIFT RIGHT THRU CARRY
LOAD D
OUT
IN ADDR F4
CS
SCLK
D
IN
D
OUT
C0
SCK
MOSI
MISO
ANALOG
INPUTS
LTC1283
MC68HC05C4
MC68HC11
LTC1283 AI13
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| LTC1283CS | 3V Single Chip 10-Bit Data Acquisition System |
| LTC1283 | 3V Single Chip 10-Bit Data Acquisition System(3V，單片，10位數(shù)據(jù)采集系統(tǒng)) |
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| LTC1286C | Micropower Sampling 12-Bit A/D Converters In S0-8 Packages |
| LTC1286IN8 | Micropower Sampling 12-Bit A/D Converters In S0-8 Packages |
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