參數(shù)資料
型號: LTC1283CN
廠商: Linear Technology
文件頁數(shù): 7/24頁
文件大?。?/td> 0K
描述: IC DATA ACQ SYS 10BIT 3V 20-DIP
標準包裝: 18
類型: 數(shù)據(jù)采集系統(tǒng)(DAS)
分辨率(位): 10 b
采樣率(每秒): 15k
數(shù)據(jù)接口: 串行,并聯(lián)
電壓電源: 雙 ±
電源電壓: ±3.3V,3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 20-DIP(0.300",7.62mm)
供應商設備封裝: 20-PDIP
包裝: 管件
15
LTC1283
1283fb
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S
A
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PPLICATI
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I FOR ATIO
Hardware and Software Interface to TI TMS70C42 Processor
Texas Instruments TMS70C42
The TMS70C42 transfers serial data in 8-bit increments,
LSB-first. To accommodate this, the LTC1283 is pro-
grammed for 16-bit word length and LSB-first format. The
10-bit output data is received by the processor as two
8-bit bytes, LSB-first. The LTC1283 fills the final 6 unused
bits (after the MSB) with zeroes.
DOUT from LTC1283 stored in TMS70C42 RAM
LABEL
MNEMONIC
DESCRIPTION
START
DINT
DISABLES ALL INTERRUPTS
MOVP
% > 2A, P0
DISABLE INTERRUPT FLAGS
MOVP
% > 02, P16
DISABLE INTERRUPT FLAGS
MOV
% > 60, B
ADDRESS OF STACK
LDSP
PUT ADDRESS INTO POINTER
MOVP
% > DF, P5
CONFIGURE PORT A
MOVP
% > 08, P6
ENABLE Tx BY SETTING B3 = 1
MOVP
% > 40, P21
RESET THE SERIAL PORT
MOVP
% > 0C, P20
CONFIGURE THE SERIAL PORT
MOVP
% > 00, P24
TURN START BIT OFF
MOVP
% > 00, P21
ENABLE THE SERIAL PORT
MOVP
% > 00, P23
SET SCLK RATE (TIMER 3)
MOVP
% > C0, P24
START TIMER
LOOP
MOV
% > DF, A
LOAD DIN WORD IN A
CALL
SXTNBIT
ROUTINE THAT SHIFTS DATA
MOV
B, R5
PUT FIRST 8 LSBs IN R5
MOV
A, R6
PUT MSBs IN R6
SXTNBIT
ANDP
% > FE, P4
A0 CLEARED (CS GOES LOW)
MOVP
A, P26
PUT DIN INTO TXBUF
LABEL
MNEMONIC
DESCRIPTION
MOVP
% > 40, P24
SCLK OFF (TIMER 3 DISABLED)
MOVP
% > 17, P21
ENABLE SERIAL PORT
MOVP
% > C0, P24
SCLK ON (TRANSFER BEGINS)
MOVP
% > 16, P21
TXEN GOES LOW
MOV
% > 02, A
LOAD COUNTER
WAIT1
DJNZ
A, WAIT1
LOOP WHILE SHIFT OCCURS
NOP
DELAY
MOVP
P25, B
PUT DOUT IN B
MOVP
A, P26
LOAD TXBUF
MOVP
% > 40, P24
SCLK OFF (TIMER 3 DISABLE)
MOVP
% > 17, P21
ENABLE SERIAL PORT
MOVP
% > C0, P24
SCLK ON (TRANSFER BEGINS)
MOVP
% > 16, P21
TXEN GOES LOW
MOV
% > 02, A
LOAD COUNTER
WAIT2
DJNZ
A, WAIT2
LOOP WHILE SHIFT OCCURS
NOP
DELAY
MOVP
P25, A
PUT DOUT IN A
ORP
% > 01, P4
A0 SET (CS GOES HIGH)
RETS
RETURN TO MAIN PROGRAM
Signetics 83CL410
To interface to the 83CL410, (a 3V version of the 80C51)
the LTC1283 is programmed for MSB-first format and 10-
bit word length. The 83CL410 generates CS, SCLK and DIN
on three port lines and reads DOUT on the fourth.
Parallel Port Microprocessors
When interfacing the LTC1283 to an MPU which has a
parallel port, the serial signals are created on the port with
software. Three MPU port lines are programmed to create
the CS, SCLK and DIN signals for the LTC1283. A fourth
port line reads the DOUT line. An example is made of the
Signetics 83CL410.
Hardware and Software Interface to Signetics 83CL410 Processor
DOUT
DIN
SCLK
CS
ACLK
P1.1
P1.2
P1.3
P1.4
ALE
ANALOG
INPUTS
LTC1283
83CL410
LTC1283 AI17
CS
SCLK
DIN
DOUT
AO
SCLK
TXD
RXD
LTC1283
TMS70C42
LTC1283 AI15
ANALOG
INPUTS
76
5
4
3
2
1
0
LSB
FILL WITH ZEROES
BYTE 1
LTC1283 AI16
00
0
00
9
8
BYTE 2
MSB
DOUT from LTC1283 stored in 83CL410 RAM
B9
B8
B7
B6
B5
B4
B3
B2
MSB*
LSB
LTC1283 AI18
B1
B2
0
R2
R3
*B9 IS MSB IN UNIPOLAR OR
SIGN BIT IN BIPOLAR
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