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參數(shù)資料
| 型號： | LTC1287CIN |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 3V Single Chip 12-Bit Data Acquisition System |
| 中文描述： | 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 324K |
| 代理商： | LTC1287CIN |
LTC1287
13
U
S
A
O
PPLICATI
IU
U
Figures 13 and 14 show examples of both adequate and
poor settling. Using a slower CLK will allow more time
for the reference to settle. Even at the maximum CLK
rate of 500kHz most references and op amps can be
made to settle within the 2
μ
s bit time. For example an
LT1019 used in the shunt mode with a 10
μ
F bypass
capacitor will settle adequately. To minimize power an
LT1004-2.5 can be used with a 10
μ
F bypass capacitor.
For lower value references the LT1004-1.2 with a 10
μ
F
bypass capacitor can be used.
Reduced Reference Operation
The effective resolution of the LTC1287 can be in-
creased by reducing the input span of the converter.
The LTC1287 exhibits good linearity over a range of
reference voltages (seeTypical Performance Charac-
teristics curves of Change in Linearity vs Reference
Voltage). Care must be taken when operating at low
values of V
REF
because of the reduced LSB step size and
the resulting higher accuracy requirement placed on
the converter. Offset and Noise are factors that must be
considered when operating at low V
REF
values.
Offset with Reduced V
REF
The offset of the LTC1287 has a larger effect on the
output code when the A/D is operated with a reduced
reference voltage. The offset (which is typically a fixed
voltage) becomes a larger fraction of an LSB as the size
of the LSB is reduced. The Typical Performance Char-
acteristics curve of Unadjusted Offset Error vs Refer-
ence Voltage shows how offset in LSBs is related to
reference voltage for a typical value of V
OS
. For
example a V
OS
of 0.1mV, which is 0.2LSB with a 2.5V
reference becomes 0.4LSB with a 1.25 reference. If
this offset is unacceptable, it can be corrected digitally
by the receiving system or by offsetting the –IN input to
the LTC1287.
Noise with Reduced V
REF
The total input referred noise of the LTC1287 can be
reduced to approximately 200
μ
V peak-to-peak using a
ground plane, good bypassing, good layout techniques
and minimizing noise on the reference inputs. This
Figure 14. Poor Reference Settling Can Cause A/D Errors
Figure 13. Adequate Reference Settling
HORIZONTAL: 1
μ
s/DIV
V
V
HORIZONTAL: 10
μ
s/DIV
conversion (every CLK cycle) a capacitive current spike
will be generated on the reference pin by the A/D. These
current spikes settle quickly and do not cause a prob-
lem. If slow settling circuitry is used to drive the
reference input, take care to insure that transients
caused by these current spikes settle completely during
each bit test of the conversion.
Figure 12. Reference Input Equivalent Circuit
R
ON
8pF – 40pF
LTC1287
REF+
14
R
OUT
V
REF
EVERY CLK CYCLE
13
GND
LTC 1287 F12
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