參數(shù)資料
型號(hào)： LTC1289BCSW#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 0K
描述： IC DATA ACQ SYS 12BIT 3V 20-SOIC
標(biāo)準(zhǔn)包裝： 1,000
類型： 數(shù)據(jù)采集系統(tǒng)（DAS）
分辨率（位）： 12 b
采樣率（每秒）： 25k
數(shù)據(jù)接口： 串行，并聯(lián)
電壓電源： 雙 ±
電源電壓： ±3.3V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 20-SOIC
包裝： 帶卷 (TR)
17
LTC1289
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S
A
O
PPLICATI
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I FOR ATIO
3. Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1289 have
capacitive switching input current spikes. These current
spikes settle quickly and do not cause a problem. How-
ever, if large source resistances are used or if slow settling
op amps drive the inputs, care must be taken to insure that
the transients caused by the current spikes settle com-
pletely before the conversion begins.
Source Resistance
The analog inputs of the LTC1289 look like a 100pF
capacitor (CIN) is series with a 1500 resistor (RON) as
shown in Figure 9. This value for RON is for VCC = 2.7V.
With larger supply voltages RON will be reduced. For
example with VCC = 2.7V and V –= –2.7V RON becomes
500
. CIN gets switched between the selected “+” and “–”
inputs once during each conversion cycle. Large external
source resistors and capacitances will slow the settling of
Figure 10. “+” and “–” Input Settling Windows
the inputs. It is important that the overall RC time con-
stants be short enough to allow the analog inputs to
completely settle within the allotted time.
“+” Input Settling
This input capacitor is switched onto the “+” input during
the sample phase (tSMPL, see Figure 10). The sample
phase starts at the 4th SCLK cycle and lasts until the falling
edge of the last SCLK (the 8th, 12th or 16th SCLK cycle
depending on the selected word length). The voltage on
the “+” input must settle completely within this sample
time. Minimizing RSOURCE+ and C1 will improve the input
settling time. If large “+” input source resistance must be
used, the sample time can be increased by using a slower
SCLK frequency or selecting a longer word length. With
the minimum possible sample time of 4
s, RSOURCE+ < 2k
and C1 < 20pF will provide adequate settling.
“–” Input Settling
At the end of the sample phase the input capacitor switches
to the “–” input and the conversion starts (see Figure 10).
During the conversion, the “+” input voltage is effectively
“held” by the sample and hold and will not affect the
conversion result. However, it is critical that the “–” input
voltage be free of noise and settle completely during the
first four ACLK cycles of the conversion time. Minimizing
RSOURCE– and C2 will improve settling time. If large “–”
input source resistance must be used, the time allowed for
Figure 9. Analog Input Equivalent Circuit
SCLK
CS
“+” INPUT
ACLK
1289 AIF10
1
234
MUX ADDRESS
SHIFTED IN
tSMPL
LAST SCLK (8TH, 12TH OR 16TH DEPENDING ON WORK LENGTH)
1
234
1ST BIT TEST
“–” INPUT MUST SETTLE
DURING THIS TIME
SAMPLE
HOLD
“+” INPUT
MUST SETTLE
DURING THIS TIME
“–” INPUT
4TH SCLK
RON = 1.5k
LAST SCLK
CIN =
100pF
LTC1289
“+”
INPUT
RSOURCE +
VIN +
C1
“–”
INPUT
RSOURCE –
VIN –
C2
LTC1289 AIF09
相關(guān)PDF資料
PDF描述
LTC1289BCSW#TR IC DATA ACQ SYS 12BIT 3V 20SOIC
VE-B5X-MY-S CONVERTER MOD DC/DC 5.2V 50W
V150A5M300B3 CONVERTER MOD DC/DC 5V 300W
LTC1289BCSW#PBF IC DATA ACQ SYS 12BIT 3V 20-SOIC
LTC1289BCSW IC DATA ACQ SYS 12BIT 3V 20-SOIC
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