參數(shù)資料
型號: LTC1290BIJ
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: Single Chip 12-Bit Data Acquisition System
中文描述: 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20
封裝: 0.300 INCH, HERMETIC SEALED, CERDIP-20
文件頁數(shù): 12/28頁
文件大?。?/td> 381K
代理商: LTC1290BIJ
12
LTC 1290
U
S
A
O
PPLICATI
W
U
I FOR ATIO
U
MSB-First/LSB-First Format (MSBF)
The output data of the LTC1290 is programmed for MSB-
first or LSB-first sequence using the MSBF bit. For MSB
first output data the input word clocked to the LTC1290
should always contain a logical one in the sixth bit location
(MSBF bit). Likewise for LSB-first output data the input
word clocked to the LTC1290 should always contain a zero
in the MSBF bit location. The MSBF bit affects only the
order of the output data word. The order of the input word
is unaffected by this bit.
MSBF
0
1
OUTPUT FORMAT
LSB First
MSB First
Word Length (WL1, WL0) and Power Shutdown
The last two bits of the input word (WL1 and WL0)
program the output data word length and the power
shutdown feature of the LTC1290. Word lengths of 8, 12
or 16 bits can be selected according to the following table.
The WL1 and WL0 bits in a given D
IN
word control the
length of the present, not the next, D
OUT
word. WL1 and
WL0 are never “don’t cares” and must be set for the
correct D
OUT
word length even when a “dummy” D
IN
word
is sent. On any transfer cycle, the word length should be
made equal to the number of SCLK cycles sent by the
MPU. Power down will occur when WL1 = 0 and WL0 = 1
is selected. The previous conversion result will be clocked
out as a 10 bit word so a “dummy”conversion is required
before powering down the LTC1290. Conversions are
resumed once CS goes low or an SCLK is applied, if CS is
already low.
WL1
WL0
OUTPUT WORD LENGTH
0
0
1
1
0
1
0
1
8-Bits
Power Shutdown
12-Bits
16-Bits
Deglitcher
A deglitching circuit has been added to the Chip Select
input of the LTC1290 to minimize the effects of errors
caused by noise on that input. This circuit ignores changes
in state on the CS input that are shorter in duration than
one ACLK cycle. After a change of state on the CS input, the
LTC1290 waits for two falling edge of the ACLK before
recognizing a valid chip select. One indication of CS
recognition is the D
OUT
line becoming active (leaving the
Hi-Z state). Note that the deglitching applies to both the
rising and falling CS edges.
CS Low During Conversion
In the normal mode of operation, CS is brought high
during the conversion time. The serial port ignores any
SCLK activity while CS is high. The LTC1290 will also
operate with CS low during the conversion. In this mode,
SCLK must remain low during the conversion as shown in
the following figure. After the conversion is complete, the
D
OUT
line will become active with the first output bit. Then
the data transfer can begin as normal.
Low CS Recognized Internally
High CS Recognized Internally
D
OUT
CS
LTC1290 AI07
ACLK
VALID OUTPUT
HI-Z
D
OUT
CS
LTC1290 AI06
ACLK
VALID OUTPUT
HI-Z
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