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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | LTC1290CCN |
| 寤犲晢锛� | Linear Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 11/32闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DATA ACQ SYS 12BIT 20-DIP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 18 |
| 椤炲瀷锛� | 鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛�锛孉DC |
| 鍒嗚鲸鐜囷紙浣嶏級锛� | 12 b |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 50k |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶锛屽苟鑱�(li谩n) |
| 闆诲闆绘簮锛� | 闆� ± |
| 闆绘簮闆诲锛� | ±5 V锛�5 V |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 閫氬瓟 |
| 灏佽/澶栨锛� | 20-DIP锛�0.300"锛�7.62mm锛� |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 20-PDIP |
| 鍖呰锛� | 绠′欢 |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)鐣�(d膩ng)鍓嶇11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)绗�25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)绗�28闋�(y猫)绗�29闋�(y猫)绗�30闋�(y猫)绗�31闋�(y猫)绗�32闋�(y猫)
19
LTC1290
1290fe
V鈥�
22
F
TANTALUM
VCC
LTC1290 F06
0.1
F
CERAMIC
DISK
ANALOG
GROUND
PLANE
1
10
20
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Figure 6. Example Ground Plane for the LTC1290
Figure 6 shows an example of an ideal ground plane design
for a two-sided board. Of course, this much ground plane
will not always be possible, but users should strive to get
as close to this ideal as possible.
2. Bypassing
For good performance, VCC must be free of noise and
ripple. Any changes in the VCC voltage with respect to
analog ground during a conversion cycle can induce
errors or noise in the output code. VCC noise and ripple can
be kept below 0.5mV by bypassing the VCC pin directly to
the analog ground plane with a 22
F tantalum capacitor
and leads as short as possible. The lead from the device to
the VCC supply should also be kept to a minimum and the
VCC supply should have a low output impedance such as
that obtained from a voltage regulator (e.g., LT1761).
Figures 7 and 8 show the effects of good and poor VCC
bypassing.
3. Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1290 have
capacitive switching input current spikes. These current
Figure 7. Poor VCC Bypassing.
Noise and Ripple Can Cause A/D Errors
VERTICAL:
0.5mV/DIV
HORIZONTAL: 10
s/DIV
CS
VCC
Figure 8. Good VCC Bypassing Keeps
Noise and Ripple on VCC Below 1mV
HORIZONTAL: 10
s/DIV
VERTICAL:
0.5mV/DIV
spikes settle quickly and do not cause a problem. How-
ever, if large source resistances are used or if slow settling
op amps drive the inputs, care must be taken to insure that
the transients caused by the current spikes settle com-
pletely before the conversion begins.
Source Resistance
The analog inputs of the LTC1290 look like a 100pF
capacitor (CIN) in series with a 500 resistor (RON) as
shown in Figure 9. CIN gets switched between the selected
鈥�+鈥� and 鈥溾€撯€� inputs once during each conversion cycle. Large
external source resistors and capacitances will slow the
settling of the inputs. It is important that the overall RC time
constants be short enough to allow the analog inputs to
completely settle within the allowed time.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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| VI-B1L-IU-F3 | CONVERTER MOD DC/DC 28V 200W |
| M83723/75W14046 | CONN PLUG 4POS STRAIGHT W/SCKT |
| AD7890BRZ-4REEL | IC DAS 12BIT 8CH 24-SOIC |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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| LTC1290CCN#PBF | 鍔熻兘鎻忚堪:IC DATA ACQ SYS 12BIT 20-DIP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Data Converter Basics 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- 椤炲瀷:闆绘(j墨)鎺у埗 鍒嗚鲸鐜囷紙浣嶏級:12 b 閲囨ǎ鐜囷紙姣忕锛�:1M 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶锛屽苟鑱�(li谩n) 闆诲闆绘簮:鍠浕婧� 闆绘簮闆诲:2.7 V ~ 3.6 V锛�4.5 V ~ 5.5 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:100-TQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:100-TQFP锛�14x14锛� 鍖呰:鍓垏甯� (CT) 鍏跺畠鍚嶇ū:296-18373-1 |
| LTC1290CCNPBF | 鍒堕€犲晢:Linear Technology 鍔熻兘鎻忚堪:ADC SAR 50ksps 12-Bit Serial PDIP20 |
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