Voltage Waveforms for DOUT Rise and Fall Times, t" />
參數(shù)資料
型號: LTC1291BCN8#PBF
廠商: Linear Technology
文件頁數(shù): 18/20頁
文件大?。?/td> 0K
描述: IC DATA ACQ SYSTEM 12BIT 8-DIP
標準包裝: 50
類型: 數(shù)據(jù)采集系統(tǒng)(DAS)
分辨率(位): 12 b
數(shù)據(jù)接口: 串行,并聯(lián)
電壓電源: 單電源
電源電壓: 5V
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 8-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 8-PDIP
包裝: 管件
7
LTC1291
1291fa
TEST CIRCUITS
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
Voltage Waveforms for DOUT Delay Time, tdDO
CLK
DOUT
0.8V
tdDO
0.4V
2.4V
1291 TC03
DOUT
0.4V
2.4V
tr
tf
1291 TC04
Voltage Waveforms for ten
DOUT
CS
START
0.8V
ten
B11
1291 TC07
1
2
34
5
DIN
CLK
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
being transmitted on the falling CLK edge and captured on
the rising CLK edge in both transmitting and receiving
systems.
The LTC1291 is a data acquisition component which
contains the following functional blocks:
1. 12-bit successive approximation capacitive A/D
converter
2. Analog multiplexer (MUX)
3. Sample-and-hold (S/H)
4. Synchronous, half duplex serial interface
5. Control and timing logic
DIGITAL CONSIDERATIONS
Serial Interface
The LTC1291 communicates with microprocessors and
other external circuitry via a synchronous, half duplex,
4-wire serial interface (see Operating Sequence). The
clock (CLK) synchronizes the data transfer with each bit
Figure 1
The input data is first received and then the A/D conversion
result is transmitted (half duplex). Because of the half
duplex operation DIN and DOUT may be tied together
allowing transmission over just 3 wires: CS, CLK and
CS
DOUT 1
DIN 1
SHIFT MUX
ADDRESS IN
1 NULL
BIT
SHIFT A/D CONVERSION
RESULT OUT
1291 F01
DIN 2
DOUT 2
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