參數(shù)資料
型號(hào)： LTC1291BMJ8
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： Single Chip 12-Bit Data Acquisition System
中文描述： 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP8
封裝： CERAMIC, DIP-8
文件頁(yè)數(shù)： 8/20頁(yè)
文件大小： 376K
代理商： LTC1291BMJ8
8
LTC1291
U
S
A
DATA (D
IN
/D
OUT
). Data transfer is initiated by a falling chip
select (CS) signal. After CS falls the LTC1291 looks for a
start bit. After the start bit is received a 4-bit input word is
shifted into the D
IN
input which configures the LTC1291
and starts the conversion. After one null bit, the result of
O
PPLICATI
IU
U
the conversion appears MSB-first on the D
OUT
line. The
conversion result is output, bit by bit, as the conversion is
performed. At the end of the data exchange CS should be
brought high. This resets the LTC1291 in preparation for
the next data exchange.
Operating Sequence
(Example: Differential Inputs (CH0+, CH1–))
MSB-FIRST DATA (MSBF = 1)
t
CYC
CS
START
MSBF
t
SMPL
HI-Z
FILLED WITH ZEROES
B0
B1
D
IN
PS
SGL/
DIFF
ODD/
SIGN
D
OUT
t
CONV
HI-Z
B11
t
CONV
B1
B0
B1
B11
FILLED WITH
ZEROES
CLK
DON'T
CARE
LSB-FIRST DATA (MSBF = 0)
t
CYC
DON’T
CARE
DON'T CARE
CS
D
IN
D
OUT
CLK
START
PS
MSBF
ODD/
SIGN
t
SMPL
SGL/
DIFF
DON'T CARE
1291 AI03
B11
CS
START
MSBF
HI-Z
FILLED WITH
ZEROES
D
IN
PS
SGL/
DIFF
ODD/
SIGN
D
OUT
B11
B0
CLK
DON'T CARE
1291 AI04
SHUTDOWN*
NEW CONVERSION BEGINS
START
MSBF
PS
SGL/
DIFF
ODD/
SIGN
HI-Z
DATA NOT VALID
REQUEST POWER SHUTDOWN
* STOPPING THE CLOCK WILL HELP REDUCE POWER CONSUMPTION
CS CAN BE BROUGHT HIGH ONCE D
IN
HAS BEEN CLOCKED IN
Power Shutdown Operating Sequence
(Example: Differential Inputs (CH0+, CH1–) and MSB-First Data)
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