- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377740 > LTC1291DC (Linear Technology Corporation) Single Chip 12-Bit Data Acquisition System PDF資料下載
參數(shù)資料
| 型號： | LTC1291DC |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Single Chip 12-Bit Data Acquisition System |
| 中文描述： | 單芯片12位數(shù)據(jù)采集系統(tǒng) |
| 文件頁數(shù)： | 15/20頁 |
| 文件大小： | 376K |
| 代理商： | LTC1291DC |
15
LTC1291
U
S
A
O
PPLICATI
U
U
or GND lead will cause gain errors and offset errors (Figure
7). For the best performance the LTC1291 should be
soldered directly to the PC board. If the source can not be
placed next to the pin and the gain parameter is important
the pin should be Kelvin-sensed to eliminate parasitic
resistances due to long PC traces. For example, 0.1
of
resistance in the V
CC
lead can typically cause 0.5LSB
(I
CC
×
0.1
/V
CC
) of gain error for V
CC
= 5V.
When the input MUX is selected for single-ended input the
minus terminal is connected to GND internally on the die.
Any parasitic resistance from the GND pin to the ground
plane will lead to an offset voltage (I
CC
×
R
P2
).
“+” Input Settling
The input capacitor is switched onto the “+” input during
the sample phase (t
SMPL
, see Figure 9). The sample period
is 2.5 CLK cycles before a conversion starts. The voltage
on the “+” input must settle completely within the sample
period. Minimizing R
SOURCE
+ and C1 will improve the
settling time. If large “+” input source resistance must be
used, the sample time can be increased by using a slower
CLK frequency. With the minimum possible sample time
of 2.5
μ
s,
R
SOURCE
+ < 1.0k and C1 < 20pF will provide
adequate settle time.
“–” Input Settling
At the end of the sample phase the input capacitor switches
to the “–” input and the conversion starts (see Figure 9).
During the conversion, the “+” input voltage is effectively
“held” by the sample-and-hold and will not affect the
conversion result. It is critical that the “–” input voltage be
free of noise and settle completely during the first CLK
cycle of the conversion. Minimizing R
SOURCE
– and C2 will
improve settling time. If large “–” input source resistance
must be used, the time can be extended by using a slower
CLK frequency. At the maximum CLK frequency of 1MHz,
R
SOURCE
– < 250
and C2 < 20pF will provide adequate
settling.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settles within the allowed time
(see Figure 9). Again the “+” and “–” input sampling times
can be extended as described above to accommodate
slower op amps. Most op amps including the LT1006 and
LT1013 single supply op amps can be made to settle well
even with the minimum settling windows of 2.5
μ
s (“+”
input) and 1
μ
s (“–” input) that occurs at the maximum
clock rate of 1MHz. Figures 10 and 11 show examples
adequate and poor op amp settling.
and capacitances will slow the settling of the inputs. It is
important that the overall RC time constant is short
enough to allow the analog inputs to settle completely
within the allowed time.
Figure 7. Parasitic Resistance in the V
CC
and GND Leads
Source Resistance
The analog inputs of the LTC1291 look like a 100pF
capacitor (C
IN
) in series with a 500
resistor (R
ON
). C
IN
gets switched between “+” and “–” inputs once during
each conversion cycle. Large external source resistors
Figure 8. Analog Input Equivalent Circuit
–
+
REF
+
REF
–
D/A
5V
V
CC
GND
LTC1291 F07
R
P1
R
P2
LTC1291
3RD CLK
↑
R
ON
= 500
C
=
100pF
LTC1291
“+”
INPUT
R
SOURCE
+
V
IN
+
C1
“–”
INPUT
R
SOURCE
–
V
IN
–
C2
LTC1291 F08
5TH CLK
↓
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC1291DI | Single Chip 12-Bit Data Acquisition System |
| LTC1291DIN8 | Single Chip 12-Bit Data Acquisition System |
| LTC1291DM | Single Channel Codec W/Hybrid Op Amps & Speaker Driver 48-LQFP -40 to 85 |
| LTC1291DMJ8 | RF/Coaxial Connector; RF Coax Type:BNC; Contact Termination:Crimp; Body Style:Straight Plug; RG Cable Type:Belden 1505A RoHS Compliant: Yes |
| LTC1291BIN8 | Single Chip 12-Bit Data Acquisition System |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC1291DCN8 | 功能描述:IC DATA ACQ SYSTEM 12BIT 8-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
| LTC1291DCN8#PBF | 功能描述:IC DATA ACQ SYSTEM 12BIT 8-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Basics 標(biāo)準(zhǔn)包裝:1 系列:- 類型:電機(jī)控制 分辨率（位）:12 b 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，并聯(lián) 電壓電源:單電源 電源電壓:2.7 V ~ 3.6 V，4.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:100-TQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:剪切帶 (CT) 其它名稱:296-18373-1 |
| LTC1291DMJ8/883 | 制造商:Linear Technology 功能描述:ADC Single SAR 54ksps 12-bit Serial 8-Pin CDIP 制造商:Linear Technology 功能描述:Single ADC SAR 54ksps 12-bit Serial 8-Pin CDIP |
| LTC1292BCJ8 | 制造商:Linear Technology 功能描述:ADC Single SAR 60ksps 12-bit Serial 8-Pin CDIP |
| LTC1292BCN8 | 功能描述:IC DATA ACQ SYSTEM 12BIT 8-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。