參數(shù)資料
型號(hào)： LTC1291DI
廠商： Linear Technology Corporation
英文描述： Single Chip 12-Bit Data Acquisition System
中文描述： 單芯片12位數(shù)據(jù)采集系統(tǒng)
文件頁(yè)數(shù)： 9/20頁(yè)
文件大?。?/td> 376K
代理商： LTC1291DI
9
LTC1291
Input Data Word
The 4-bit data word is clocked into the D
IN
pin on the rising
edge of the clock after chip select goes low and the start
bit has been recognized. Further inputs on the D
IN
pin are
then ignored until the next CS cycle. The input word is
defined as follows:
Start Bit
The first “l(fā)ogical one” clocked into the D
IN
input after CS
goes low is the start bit. The start bit initiates the data
transfer and all leading zeroes which precede this logical
one will be ignored. After the start bit is received the
remaining bits of the input word will be clocked in. Further
inputs on the D
IN
pin are then ignored until the next CS
cycle.
MUX Address
The bits of the input word following the START BIT assign
the MUX configuration for the requested conversion. For
a given channel selection, the converter will measure the
voltage between the two channels indicated by the “+” and
“–” signs in the selected row of the following table. In
single-ended mode, all input channels are measured with
respect to GND. Only the “+” inputs have sample-and-
holds. Signals applied at the “–” inputs must not change
more than the required accuracy during the conversion.
Figure 2. Input Data Word
U
S
A
O
PPLICATI
U
U
START
SGL/
DIFF
ODD/
SIGN
MSBF
MUX ADDRESS
MSB-FIRST/
LSB-FIRST
POWER
SHUTDOWN
1291 F02
PS
Multiplexer Channel Selection
MUX ADDRESS
SGL/DIFF
1
1
0
0
CHANNEL #
0
+
ODD/SIGN
0
1
0
1
1
GND
–
–
+
–
+
+
–
MSB-First/LSB-First (MSBF)
The output data of the LTC1291 is programmed for MSB-
first or LSB-first sequence using the MSBF bit. When the
MSBF bit is a logical one, data will appear on the D
OUT
line
in MSB-first format. Logical zeroes will be filled in indefi-
nitely following the last data bit to accommodate longer
word lengths required by some microprocessors. When
the MSBF bit is a logical zero, LSB-first data will follow the
normal MSB-first data on the D
OUT
line (see Operating
Sequence).
Power Shutdown
The power shutdown feature of the LTC1291 is activated
by making the PS bit a logical zero. If CS remains low after
the PS bit has been received, a 12-bit D
OUT
word with all
logical ones will be shifted out followed by logical zeroes
until CS goes high. Then the D
OUT
line will go into its high
impedance state. The LTC1291 will remain in the shut-
down mode until the next CS cycle. There is no warm-up
or wait period required after coming out of the power
shutdown cycle so a conversion can commence after CS
goes low (see Power Shutdown Operating Sequence).
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