參數資料
型號: LTC1292CCN8
廠商: Linear Technology
文件頁數: 8/24頁
文件大?。?/td> 0K
描述: IC DATA ACQ SYSTEM 12BIT 8-DIP
標準包裝: 50
類型: 數據采集系統(DAS)
分辨率(位): 12 b
采樣率(每秒): 60k
數據接口: 串行,并聯
電壓電源: 單電源
電源電壓: 5V
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 8-DIP(0.300",7.62mm)
供應商設備封裝: 8-PDIP
包裝: 管件
16
LTC1292/LTC1297
12927fb
Figure 12. “+” and “–” Input Settling Windows for the LTC1297
“–” input voltage be free of noise and settle completely
during the first CLK cycle of the conversion. Minimizing
RSOURCE– and C2 will improve settling time. If large “–”
input source resistance must be used the time can be
extended by using a slower CLK frequency. At the maximum
CLK frequency of 1MHz, RSOURCE– < 250and C2 < 20pF
will provide adequate settling.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settles within the allowed time
(see Figures 11a, 11b, 11c and 12). Again the “+” and “–
” input sampling times can be extended as described
above to accommodate slower op amps. Most op amps
including the LT1797 and LT1677 single supply op amps
can be made to settle well even with the minimum settling
windows of 3.0
s for the LTC1292 or 6.0s for the
LTC1297 (“+” input) and 1
s (“–” input) that occurs at the
maximum clock rate of 1MHz. Figures 13 and 14 show
examples of both adequate and poor op amp settling.
VERTICAL:
5mV/DIV
HORIZONTAL: 500ns/DIV
HORIZONTAL: 20
s/DIV
Figure 13. Adequate Settling of Op Amp Driving Analog Input
VERTICAL:
5mV/DIV
Figure 14. Poor Op Amp Settling Can Cause A/D Errors
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
DOUT
CLK
B11
HI-Z
B10
LTC1292/7 F12
CS
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
tWHCS
tSMPL
(+) INPUT MUST SETTLE
DURING THIS TIME
(+) INPUT
(–) INPUT
tsuCS
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