參數(shù)資料
型號： LTC1293DMJ
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： Computer Keyboard
中文描述： 6-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP16
封裝： CERAMIC, DIP-16
文件頁數(shù)： 7/28頁
文件大?。?/td> 494K
代理商： LTC1293DMJ
7
LTC1293/LTC1294/LTC1296
PI FUU
U
#
PIN
FUNCTION
DESCRIPTION
1 – 6
7
CH0 – CH5
COM
Analog Inputs
Common
The analog inputs must be free of noise with respect to AGND.
The common pin defines the zero reference point for all single ended inputs. It must be free of noise and is
usually tied to the analog ground plane.
This is the ground for the internal logic. Tie to the ground plane.
Tie V
–
to most negative potential in the circuit (Ground in single supply applications).
AGND should be tied directly to the analog ground plane.
The reference inputs must be kept free of noise with respect to AGND.
The A/D configuration word is shifted into this input.
The A/D conversion result is shifted out of this output.
A logic low on this input enables data transfer.
This clock synchronizes the serial data transfer and controls A/D conversion rate.
This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
8
9
10
11
12
13
14
15
16
DGND
V
–
AGND
V
REF
D
IN
D
OUT
CS
CLK
V
CC
Digital Ground
Negative Supply
Analog Ground
Ref. Input
Data Input
Digital Data Output
Chip Select Input
Clock
Positive supply
LTC1293
#
PIN
FUNCTION
DESCRIPTION
1 –8
9
CH0 – CH7
COM
Analog Inputs
Common
The analog inputs must be free of noise with respect to AGND.
The common pin defines the zero reference point for all single ended inputs. It must be free of noise and is
usually tied to the analog ground plane.
This is the ground for the internal logic. Tie to the ground plane.
Tie V
–
to most negative potential in the circuit (Ground in single supply applications).
AGND should be tied directly to the analog ground plane.
The reference inputs must be kept free of noise with respect to AGND. The A/D sees a reference voltage equal
to the difference between REF
+
and REF
–
.
The A/D configuration word is shifted into this input.
The A/D conversion result is shifted out of this output.
A logic low on this input enables data transfer.
This clock synchronizes the serial data transfer and controls A/D converion rate.
These supplies must be kept free of noise and ripple by bypassing directly to the analog ground plane. AV
CC
and DV
CC
must be tied together.
10
11
12
13, 14 REF
–
, REF
+
DGND
V
–
AGND
Digital Ground
Negative Supply
Analog Ground
Ref. Inputs
15
16
17
18
19, 20 AV
CC,
DV
CC
D
IN
D
OUT
CS
CLK
Data Input
Digital Data Output
Chip Select Input
Clock
Positive Supplies
LTC1294
#
PIN
FUNCTION
DESCRIPTION
1 –8
9
CH0 – CH7
COM
Analog Inputs
Common
The analog inputs must be free of noise with respect to AGND.
The common pin defines the zero reference point for all single ended inputs. It must be free of noise and is
usually tied to the analog ground plane.
This is the ground for the internal logic. Tie to the ground plane.
Tie V
–
to most negative potential in the circuit (Ground in single supply applications).
AGND should be tied directly to the analog ground plane.
The reference inputs must be kept free of noise with respect to AGND. The A/D sees a reference voltage equal
to the difference between REF
+
and REF
–
.
The A/D configuration word is shifted into this input.
The A/D conversion result is shifted out of this output.
A logic low on this input enables data transfer.
This clock synchronizes the serial data transfer and controls A/D conversion rate.
System Shutdown Output pin will go low when power shutdown is requested.
10
11
12
13, 14 REF
–
, REF
+
DGND
V
–
AGND
Digital Ground
Negative Supply
Analog Ground
Ref. Inputs
15
16
17
18
19
D
IN
D
OUT
CS
CLK
SSO
Data Input
Digital Data Output
Chip Select Input
Clock
System Shutdown
Output
Positive Supply
20
V
CC
This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
LTC1296
相關PDF資料
PDF描述
LTC1294CIJ Single Chip 12-Bit Data Acquisition System
LTC1296DC Single Chip 12-Bit Data Acquisition System
LTC1296DCN Single Chip 12-Bit Data Acquisition System
LTC1296DCS Single Chip 12-Bit Data Acquisition System
LTC1294CC Single Chip 12-Bit Data Acquisition System
相關代理商/技術參數(shù)
參數(shù)描述
LTC1293DMJ/883 制造商:Linear Technology 功能描述:ADC Single SAR 46.5ksps 12-bit Serial 16-Pin CDIP
LTC1294BCN 功能描述:IC DATA ACQ SYSTEM 12BIT 20-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（6x6） 包裝:托盤
LTC1294BCN#PBF 功能描述:IC DATA ACQ SYSTEM 12BIT 20-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（6x6） 包裝:托盤
LTC1294BCSW 功能描述:IC DATA ACQ SYSTEM 12BIT 20-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（6x6） 包裝:托盤
LTC1294BCSW#PBF 功能描述:IC DATA ACQ SYSTEM 12BIT 20-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（6x6） 包裝:托盤
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*